Patents by Inventor Shih-Kuan Tai

Shih-Kuan Tai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6380090
    Abstract: A method and a structure for protecting a work piece in a semiconductor manufacturing process includes a cassette for mounting therein the work pieces and a sheet piece for shielding the work pieces; and a working platform for mounting thereon said cassette. Furthermore, there is a lid covering the working platform in order to prevent a contaminant from entering the cassette during the semiconductor manufacturing process so that the gate oxide loss of every wafer in the cassette will be reduced.
    Type: Grant
    Filed: October 16, 1998
    Date of Patent: April 30, 2002
    Assignee: Winbond Electrinics Corp
    Inventors: Mei-Hui Sung, Shih-Kuan Tai
  • Patent number: 6309957
    Abstract: This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to both dual and single inverse copper damascene processes to form conducting copper interconnects and contact vias simultaneously, with low dielectric constant intermetal dielectrics (IMD). The low dielectric constant material, low-K, can be of four types of material: doped oxide, organic materials, highly fluorinated films, porous materials. In addition, spin-on glass (SOG) and spin-on-dielectric (SOD) are applicable. Key to the present invention are the following process steps, that have exceptionally advanced process controls: polysilicon etching of sacrificial polysilicon, plasma ashing of the patterning photoresist, and post cleaning.
    Type: Grant
    Filed: April 3, 2000
    Date of Patent: October 30, 2001
    Assignee: Taiwan Semiconductor Maufacturing Company
    Inventors: An-Chun Tu, Shih-Kuan Tai, Tzu-Shih Yeu
  • Patent number: 6024802
    Abstract: A vapor processing method for reducing oxide material depletion includes an early step of placing a polymer-coated substrate inside a vapor process chamber (VPC), a pre-processing step of passing an inert gas into the VPC for a definite period followed by an idling period, a clearing step of passing a reactive gas carried by an inert carrier into the VPC for clearing away previously deposited polymer on the substrate, and a post-processing step of passing an inert gas into the VPC to purge any unreacted reactive gases. Thereafter, the substrate is transferred to a dry task chamber (DTC) for cleaning, wherein the cleaning includes removing any residual gases on the wafer surface. Time required for cleaning the wafer in the DTC is smaller than the total time required for pre-processing, polymer clearing and post-processing.
    Type: Grant
    Filed: July 30, 1998
    Date of Patent: February 15, 2000
    Assignee: Winbond Electronics Corp.
    Inventors: Mei-Hui Sung, Shih-Kuan Tai