Patents by Inventor Shih-Li Chen

Shih-Li Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240146205
    Abstract: A flyback power converter includes a power transformer, a first lossless voltage conversion circuit, a first low-dropout linear regulator and a secondary side power supply circuit. The first low-dropout linear regulator (LDO) generates a first operation voltage as power supply for being supplied to a sub-operation circuit. The secondary side power supply circuit includes a second lossless voltage conversion circuit and a second LDO. The second LDO generates a second operation voltage. The first operation voltage and the second operation voltage are shunted to a common node. When a first lossless conversion voltage is greater than a first threshold voltage, the second LDO is enabled to generate the second operation voltage to replace the first operation voltage as power supply supplied to the sub-operation circuit; wherein the second lossless conversion voltage is lower than the first lossless switching voltage.
    Type: Application
    Filed: September 23, 2023
    Publication date: May 2, 2024
    Inventors: Shin-Li Lin, He-Yi Shu, Shih-Jen Yang, Ta-Yung Yang, Yi-Min Shiu, Chih-Ching Lee, Yu-Chieh Hsieh, Chao-Chi Chen
  • Publication number: 20240104288
    Abstract: A system for manufacturing an integrated circuit includes a processor coupled to a non-transitory computer readable medium configured to store executable instructions. The processor is configured to execute the instructions for generating a layout design of the integrated circuit that has a set of design rules. The generating of the layout design includes generating a set of gate layout patterns corresponding to fabricating a set of gate structures of the integrated circuit, generating a cut feature layout pattern corresponding to a cut region of a first gate of the set of gate structures of the integrated circuit, generating a first conductive feature layout pattern corresponding to fabricating a first conductive structure of the integrated circuit, and generating a first via layout pattern corresponding to a first via. The cut feature layout pattern overlaps a first gate layout pattern of the set of gate layout patterns.
    Type: Application
    Filed: December 11, 2023
    Publication date: March 28, 2024
    Inventors: Shih-Wei PENG, Chih-Liang CHEN, Charles Chew-Yuen YOUNG, Hui-Zhong ZHUANG, Jiann-Tyng TZENG, Shun Li CHEN, Wei-Cheng LIN
  • Publication number: 20240096867
    Abstract: A semiconductor structure is provided and includes a first gate structure, a second gate structure, and at least one local interconnect that extend continuously across a non-active region from a first active region to a second active region. The semiconductor structure further includes a first separation spacer disposed on the first gate structure and first vias on the first gate structure. The first vias are arranged on opposite sides of the first separation spacer are isolated from each other and apart from the first separation spacer by different distances.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 21, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Charles Chew-Yuen YOUNG, Chih-Liang CHEN, Chih-Ming LAI, Jiann-Tyng TZENG, Shun-Li CHEN, Kam-Tou SIO, Shih-Wei PENG, Chun-Kuang CHEN, Ru-Gun LIU
  • Patent number: 11923413
    Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. The semiconductor structure further includes a gate structure surrounding the nanostructures and a source/drain structure attached to the nanostructures. The semiconductor structure further includes a contact formed over the source/drain structure and extending into the source/drain structure.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun Lin, Kuo-Hua Pan, Jhon-Jhy Liaw, Chao-Ching Cheng, Hung-Li Chiang, Shih-Syuan Huang, Tzu-Chiang Chen, I-Sheng Chen, Sai-Hooi Yeong
  • Patent number: 7985626
    Abstract: A manufacturing method of placing dice for a wafer level package comprises placing a plurality of dice on an elastic material, which is formed on a first base, and the elastic material of the present invention has viscosity in a first condition to adhere the plurality of dice; forming an adhesive material on a second base; adhering the plurality of dice on the adhesive material of the second base; and stripping the plurality of dice from the elastic material in a second condition.
    Type: Grant
    Filed: June 20, 2005
    Date of Patent: July 26, 2011
    Assignee: Advanced Chip Engineering Technology Inc.
    Inventors: Wen-Kun Yang, Wen-Pin Yang, Shih-li Chen
  • Patent number: 7667318
    Abstract: To pick and place standard dies on a new base for obtaining an appropriate and wider distance between dies than the original distance of dies on a wafer. The package structure has a larger size of balls array than the size of the die by fan out type package. Moreover, the die may be packaged with passive components or other dies with a side by side structure or a stacking structure.
    Type: Grant
    Filed: October 22, 2008
    Date of Patent: February 23, 2010
    Assignee: Advanced Chip Engineering Technology Inc.
    Inventors: Wen-Kun Yang, Wen-Pin Yang, Shih-Li Chen
  • Patent number: 7557437
    Abstract: To pick and place standard dice on a new base for obtaining an appropriate and wider distance between dice than the original distance of dice on a wafer. The package structure has a larger size of balls array than the size of the die by fan out type package. Moreover, the die may be packaged with passive components or other dice with a side by side structure or a stacking structure.
    Type: Grant
    Filed: November 28, 2007
    Date of Patent: July 7, 2009
    Assignee: Advanced Chip Engineering Technology Inc.
    Inventors: Wen-Kun Yang, Wen-Pin Yang, Shih-Li Chen
  • Publication number: 20090051025
    Abstract: To pick and place standard dies on a new base for obtaining an appropriate and wider distance between dies than the original distance of dies on a wafer. The package structure has a larger size of balls array than the size of the die by fan out type package. Moreover, the die may be packaged with passive components or other dies with a side by side structure or a stacking structure.
    Type: Application
    Filed: October 22, 2008
    Publication date: February 26, 2009
    Inventors: Wen-Kun Yang, Wen-Pin Yang, Shih-Li Chen
  • Patent number: 7459781
    Abstract: To pick and place standard dies on a new base for obtaining an appropriate and wider distance between dies than the original distance of dies on a wafer. The package structure has a larger size of balls array than the size of the die by fan out type package. Moreover, the die may be packaged with passive components or other dies with a side by side structure or a stacking structure.
    Type: Grant
    Filed: December 3, 2003
    Date of Patent: December 2, 2008
    Inventors: Wen-Kun Yang, Wen-Pin Yang, Shih-Li Chen
  • Publication number: 20080105967
    Abstract: To pick and place standard dice on a new base for obtaining an appropriate and wider distance between dice than the original distance of dice on a wafer. The package structure has a larger size of balls array than the size of the die by fan out type package. Moreover, the die may be packaged with passive components or other dice with a side by side structure or a stacking structure.
    Type: Application
    Filed: November 28, 2007
    Publication date: May 8, 2008
    Inventors: Wen-Kun Yang, Wen-Pin Yang, Shih-Li Chen
  • Patent number: 7262081
    Abstract: To pick and place standard dies on a new base for obtaining an appropriate and wider distance between dies than the original distance of dies on a wafer. The package structure has a larger size of balls array than the size of the die by fan out type package. Moreover, the die may be packaged with passive components or other dies with a side by side structure or a stacking structure.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: August 28, 2007
    Inventors: Wen-Kun Yang, Wen-Pin Yang, Shih-Li Chen
  • Patent number: 7224061
    Abstract: A package structure including a device, an interconnecting element, a pad and a protecting element is provided. The device connects with a first end of the interconnecting element through the pad. The protecting element covers the pad and the first end of the interconnecting element.
    Type: Grant
    Filed: August 16, 2004
    Date of Patent: May 29, 2007
    Assignee: Advanced Chip Engineering Technology Inc.
    Inventors: Wen-Kun Yang, Shih-Li Chen, Wen-Bin Sun, Ming-Hui Lin, Chao-Nan Chou, Chih-Wei Lin
  • Patent number: 7196408
    Abstract: To pick and place standard dies on a new base for obtaining an appropriate and wider distance between dies than the original distance of dies on a wafer. The package structure has a larger size of balls array than the size of the die by fan out type package. Moreover, the die may be packaged with passive components or other dies with a side by side structure or a stacking structure.
    Type: Grant
    Filed: December 12, 2005
    Date of Patent: March 27, 2007
    Inventors: Wen-Kun Yang, Wen-Pin Yang, Shih-Li Chen
  • Publication number: 20070059866
    Abstract: To pick and place standard dies on a new base for obtaining an appropriate and wider distance between dies than the original distance of dies on a wafer. The package structure has a larger size of balls array than the size of the die by fan out type package. Moreover, the die may be packaged with passive components or other dies with a side by side structure or a stacking structure.
    Type: Application
    Filed: November 13, 2006
    Publication date: March 15, 2007
    Applicant: ADVANCED CHIP ENGINEERING TECHNOLOGY INC.
    Inventors: Wen-Kun Yang, Wen-Pin Yang, Shih-Li Chen
  • Publication number: 20060091514
    Abstract: To pick and place standard dies on a new base for obtaining an appropriate and wider distance between dies than the original distance of dies on a wafer. The package structure has a larger size of balls array than the size of the die by fan out type package. Moreover, the die may be packaged with passive components or other dies with a side by side structure or a stacking structure.
    Type: Application
    Filed: December 12, 2005
    Publication date: May 4, 2006
    Inventors: Wen-Kun Yang, Wen-Pin Yang, Shih-Li Chen
  • Publication number: 20060033196
    Abstract: A package structure including a device, an interconnecting element, a pad and a protecting element is provided. The device connects with a first end of the interconnecting element through the pad. The protecting element covers the pad and the first end of the interconnecting element.
    Type: Application
    Filed: August 16, 2004
    Publication date: February 16, 2006
    Inventors: Wen-Kun Yang, Shih-Li Chen, Wen-Bin Sun, Ming-Hui Lin, Chao-Nan Chou, Chih-Wei Lin
  • Publication number: 20050247398
    Abstract: A tool of wafer level package comprises a first base, an elastic material and a second base. The elastic material is coated on the first base, and the elastic material has viscosity in common state to adhere a plurality of dies. The second base is coated by adhesive material to adhere the dies. The plurality of dies are departed from the elastic material by a special environment after adhering.
    Type: Application
    Filed: June 20, 2005
    Publication date: November 10, 2005
    Applicant: Advanced Chip Engineering Technology Inc.
    Inventors: Wen Yang, Wen Yang, Shih-li Chen
  • Publication number: 20050249945
    Abstract: A tool of wafer level package comprises a first base, an elastic material and a second base. The elastic material is coated on the first base, and the elastic material has viscosity in common state to adhere a plurality of dies. The second base is coated by adhesive material to adhere the dies. The plurality of dies are departed from the elastic material by a special environment after adhering.
    Type: Application
    Filed: May 10, 2004
    Publication date: November 10, 2005
    Inventors: Wen Kun Yang, Wen Ping Yang, Shih Li Chen
  • Publication number: 20050236696
    Abstract: To pick and place standard dies on a new base for obtaining an appropriate and wider distance between dies than the original distance of dies on a wafer. The package structure has a larger size of balls array than the size of the die by fan out type package. Moreover, the die may be packaged with passive components or other dies with a side by side structure or a stacking structure .
    Type: Application
    Filed: June 30, 2005
    Publication date: October 27, 2005
    Inventors: Wen-Kun Yang, Wen-Pin Yang, Shih-Li Chen
  • Publication number: 20050124093
    Abstract: To pick and place standard dies on a new base for obtaining an appropriate and wider distance between dies than the original distance of dies on a wafer. The package structure has a larger size of balls array than the size of the die by fan out type package. Moreover, the die may be packaged with passive components or other dies with a side by side structure or a stacking structure.
    Type: Application
    Filed: December 3, 2003
    Publication date: June 9, 2005
    Inventors: Wen-Kun Yang, Wen-Pin Yang, Shih-Li Chen