Patents by Inventor Shih Liang

Shih Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250210597
    Abstract: A panel structure including a stretchable substrate, a first flexible layer, a circuit layer, multiple light-emitting elements, a filler layer, a second flexible layer, and an element layer is disclosed. The first flexible layer includes multiple pixel islands, and the pixel islands are defined by multiple through holes. Each of the through holes passes through the first flexible layer, the filler layer, and the second flexible layer. The display structure has good continuity in structure, and optical performance of the display structure is good. A manufacturing method of a panel structure is also disclosed.
    Type: Application
    Filed: December 27, 2023
    Publication date: June 26, 2025
    Applicant: AUO Corporation
    Inventors: Shih-Liang Lin, Cheng-Liang Wang
  • Publication number: 20240348435
    Abstract: Systems and methods of generating a security key for an integrated circuit device include generating a plurality of key bits with a physically unclonable function (PUF) device. The PUF can include a random number generator that can create random bits. The random bits may be stored in a nonvolatile memory. The number of random bits stored in the nonvolatile memory allows for a plurality of challenge and response interactions to obtain a plurality of security keys from the PUF.
    Type: Application
    Filed: April 2, 2024
    Publication date: October 17, 2024
    Inventors: Shih-Lien Linus Lu, Kun-hsi Li, Shih-Liang Wang, Jonathan Tsung-Yung Chang, Yu-Der Chih, Cheng-En Lee
  • Patent number: 12109669
    Abstract: A pipe plier structure includes a first body, a second body, a pivot member, and a locking member. The first body is provided with multiple first teeth, an arc line, an axis, a first vertical line, a radius, a first angle, and a second angle. The second body is provided with multiple second teeth, multiple third teeth, a second vertical line, a first connecting line, a second connecting line, a third angle, a fourth angle, a concave face, a fifth angle, a sixth angle, a seventh angle, and an eighth angle. The pivot member is assembled with the first body and the second body. The locking member is assembled with the first body and the second body. The locking member provides an elastically restoring force to the first body and the second body after the second body is extended outward relative to the first body.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: October 8, 2024
    Inventors: Yung-Sheng Lin, Shih-Liang Huang
  • Patent number: 12091454
    Abstract: A humanized anti-neurotensin receptor 1 (NTSR1) antibody or an antigen-binding fragment thereof. Also, a method for treating, prophylactic treating and/or preventing diseases and/or disorders caused by or related to NTSR1 activity and/or signaling, and a method or kit for detecting NTSR1 in a sample.
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: September 17, 2024
    Assignees: DEVELOPMENT CENTER FOR BIOTECHNOLOGY, NATIONAL HEALTH RESEARCH INSTITUTES
    Inventors: Cheng-Chou Yu, Shu-Ping Yeh, Chao-Yang Huang, Szu-Liang Lai, Shih-Liang Hsiao, Mei-Ling Hou, Tzung-Jie Yang, Wei-Ting Sun, Liang-Yu Hsia, Andrew Yueh, Chiung-Tong Chen, Ren-Huang Wu, Pei-Shan Wu, Han-Shu Hu, Tzu-Chin Wu, Jia-Ni Tian
  • Publication number: 20240218062
    Abstract: A humanized anti-neurotensin receptor 1 (NTSR1) antibody or an antigen-binding fragment thereof. Also, a method for treating, prophylactic treating and/or preventing diseases and/or disorders caused by or related to NTSR1 activity and/or signaling, and a method or kit for detecting NTSR1 in a sample.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Applicants: DEVELOPMENT CENTER FOR BIOTECHNOLOGY, NATIONAL HEALTH RESEARCH INSTITUTES
    Inventors: CHENG-CHOU YU, SHU-PING YEH, CHAO-YANG HUANG, SZU-LIANG LAI, SHIH-LIANG HSIAO, MEI-LING HOU, TZUNG-JIE YANG, WEI-TING SUN, LIANG-YU HSIA, ANDREW YUEH, CHIUNG-TONG CHEN, REN-HUANG WU, PEI-SHAN WU, HAN-SHU HU, TZU-CHIN WU, JIA-NI TIAN
  • Patent number: 11962693
    Abstract: Systems and methods of generating a security key for an integrated circuit device include generating a plurality of key bits with a physically unclonable function (PUF) device. The PUF can include a random number generator that can create random bits. The random bits may be stored in a nonvolatile memory. The number of random bits stored in the nonvolatile memory allows for a plurality of challenge and response interactions to obtain a plurality of security keys from the PUF.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Lien Linus Lu, Kun-hsi Li, Shih-Liang Wang, Jonathan Tsung-Yung Chang, Yu-Der Chih, Cheng-En Lee
  • Publication number: 20240113142
    Abstract: An image sensor includes a group of sensor units, a color filter layer disposed within the group of sensor units, and a dielectric structure and a metasurface disposed corresponding to the color filter layer. The metasurface includes a plurality of peripheral nanoposts located at corners of the group of sensor units from top view, respectively, a central nanopost enclosed by the plurality of peripheral nanoposts, and a filling material laterally surrounding the plurality of peripheral nanoposts and the central nanopost. The central nanopost is offset from a center point of the group of sensor units by a distance from top view.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Inventors: Po-Han FU, Wei-Ko WANG, Shih-Liang KU, Chin-Chuan HSIEH
  • Patent number: 11946802
    Abstract: An ambient light sensor includes a substrate, a metasurface disposed on the substrate, and an aperture layer disposed on the substrate. The metasurface includes a plurality of nanostructures and a filling layer laterally surrounding the plurality of nanostructures. The aperture layer laterally separates the metasurface into a plurality of sub-meta groups.
    Type: Grant
    Filed: March 29, 2023
    Date of Patent: April 2, 2024
    Assignee: VISERA TECHNOLOGIES COMPANY LIMITED
    Inventors: Shih-Liang Ku, Zi-Han Liao, Chun-Wei Huang
  • Publication number: 20240053195
    Abstract: An ambient light sensor includes a substrate, a metasurface disposed on the substrate, and an aperture layer disposed on the substrate. The metasurface includes a plurality of nanostructures and a filling layer laterally surrounding the plurality of nanostructures. The aperture layer laterally separates the metasurface into a plurality of sub-meta groups.
    Type: Application
    Filed: March 29, 2023
    Publication date: February 15, 2024
    Inventors: Shih-Liang KU, Zi-Han LIAO, Chun-Wei HUANG
  • Publication number: 20240021639
    Abstract: A manufacturing method includes the following operations. A lens layer is formed above a substrate. A patterned hard mask layer is formed on the lens layer. The lens layer is etched to transfer a pattern of the patterned hard mask layer to the lens layer such that a plurality of lenses are defined, wherein the lens are micro-lenses or meta-surface lenses. A cladding layer is formed to cover the plurality of lenses and the substrate. Portions of the cladding layer are etched to form a first inclined sidewall and a second inclined sidewall, wherein the first inclined sidewall is above the second inclined sidewall, wherein a projection of the first inclined sidewall on the substrate is spaced apart from a projection of the second inclined sidewall on the substrate.
    Type: Application
    Filed: May 17, 2023
    Publication date: January 18, 2024
    Inventors: Yi-Hua CHIU, Wei-Ko WANG, Shih-Liang KU
  • Patent number: 11792918
    Abstract: A co-axial structure includes a substrate, a first conductive structure, a second conductive structure, and an insulating layer. The substrate includes a first surface. The first conductive structure includes a first circuit deposited on the first surface and a first via penetrating the substrate. The second conductive structure includes a second circuit deposited on the first surface and a second via penetrating the substrate. The first via and the second via extend along a first direction. The first circuit and the second circuit extend along a second direction, and the second direction is perpendicular to the first direction. The insulating layer is located between the first via and the second via. The insulating layer includes a filler. The first conductive structure and the second conductive structure are electrically insulated. The first circuit and the second circuit are coplanar.
    Type: Grant
    Filed: November 21, 2021
    Date of Patent: October 17, 2023
    Assignee: Unimicron Technology Corp.
    Inventors: Pei-Wei Wang, Heng-Ming Nien, Ching-Sheng Chen, Yi-Pin Lin, Shih-Liang Cheng
  • Publication number: 20230321795
    Abstract: A pipe plier structure includes a first body, a second body, a pivot member, and a locking member. The first body is provided with multiple first teeth, an arc line, an axis, a first vertical line, a radius, a first angle, and a second angle. The second body is provided with multiple second teeth, multiple third teeth, a second vertical line, a first connecting line, a second connecting line, a third angle, a fourth angle, a concave face, a fifth angle, a sixth angle, a seventh angle, and an eighth angle. The pivot member is assembled with the first body and the second body. The locking member is assembled with the first body and the second body. The locking member provides an elastically restoring force to the first body and the second body after the second body is extended outward relative to the first body.
    Type: Application
    Filed: April 8, 2022
    Publication date: October 12, 2023
    Inventors: Yung-Sheng Lin, Shih-Liang Huang
  • Publication number: 20230121502
    Abstract: Systems and methods of generating a security key for an integrated circuit device include generating a plurality of key bits with a physically unclonable function (PUF) device. The PUF can include a random number generator that can create random bits. The random bits may be stored in a nonvolatile memory. The number of random bits stored in the nonvolatile memory allows for a plurality of challenge and response interactions to obtain a plurality of security keys from the PUF.
    Type: Application
    Filed: December 9, 2022
    Publication date: April 20, 2023
    Inventors: Shih-Lien Linus Lu, Kun-hsi Li, Shih-Liang Wang, Jonathan Tsung-Yung Chang, Yu-Der Chih, Cheng-En Lee
  • Patent number: 11528135
    Abstract: Systems and methods of generating a security key for an integrated circuit device include generating a plurality of key bits with a physically unclonable function (PUF) device. The PUF can include a random number generator that can create random bits. The random bits may be stored in a nonvolatile memory. The number of random bits stored in the nonvolatile memory allows for a plurality of challenge and response interactions to obtain a plurality of security keys from the PUF.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: December 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Lien Linus Lu, Kun-hsi Li, Shih-Liang Wang, Jonathan Tsung-Yung Chang, Yu-Der Chih, Cheng-En Lee
  • Publication number: 20220240368
    Abstract: A co-axial structure includes a substrate, a first conductive structure, a second conductive structure, and an insulating layer. The substrate includes a first surface. The first conductive structure includes a first circuit deposited on the first surface and a first via penetrating the substrate. The second conductive structure includes a second circuit deposited on the first surface and a second via penetrating the substrate. The first via and the second via extend along a first direction. The first circuit and the second circuit extend along a second direction, and the second direction is perpendicular to the first direction. The insulating layer is located between the first via and the second via. The insulating layer includes a filler. The first conductive structure and the second conductive structure are electrically insulated. The first circuit and the second circuit are coplanar.
    Type: Application
    Filed: November 21, 2021
    Publication date: July 28, 2022
    Inventors: Pei-Wei WANG, Heng-Ming NIEN, Ching-Sheng CHEN, Yi-Pin LIN, Shih-Liang CHENG
  • Patent number: 11314004
    Abstract: An optical filter and a method for forming the same are provided. The optical filter includes a substrate and a plurality of filter stacks formed on the substrate. Each of the plurality of filter stacks includes a higher-refractive-index layer, a medium-refractive-index layer, and a lower-refractive-index layer. The higher-refractive-index layer has a first refractive index of higher than 3.5. The medium-refractive-index layer is disposed on the higher-refractive-index layer. The medium-refractive-index layer has a second refractive index higher than 2.9 and lower than the first refractive index. The lower-refractive-index layer is disposed on the medium-refractive-index layer. The lower-refractive-index layer has a third refractive index lower than the second refractive index.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: April 26, 2022
    Assignee: VISERA TECHNOLOGIES COMPANY LIMITED
    Inventors: Yu-Jen Chen, Chung-Hao Lin, Shih-Liang Ku
  • Patent number: 11289413
    Abstract: A wiring board and a method of manufacturing the same are provided. The method includes the following steps. A substrate is provided. The substrate is perforated to form at least one through hole. A first conductive layer is integrally formed on a surface of the substrate and an inner wall of the through hole. An etch stop layer is formed on a portion of the first conductive layer on the surface of the substrate and another portion of the first conductive layer on the inner wall of the through hole. A second conductive layer is integrally formed on the etch stop layer and the first conductive layer on the inner wall of the through hole. A plug-hole column is formed by filling with a plugged-hole material in the through hole. The second conductive layer is removed. The etch stop layer is then removed.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: March 29, 2022
    Assignee: Unimicron Technology Corp.
    Inventor: Shih-Liang Cheng
  • Publication number: 20210306148
    Abstract: Systems and methods of generating a security key for an integrated circuit device include generating a plurality of key bits with a physically unclonable function (PUF) device. The PUF can include a random number generator that can create random bits. The random bits may be stored in a nonvolatile memory. The number of random bits stored in the nonvolatile memory allows for a plurality of challenge and response interactions to obtain a plurality of security keys from the PUF.
    Type: Application
    Filed: November 30, 2020
    Publication date: September 30, 2021
    Inventors: Shih-Lien Linus Lu, Kun-hsi Li, Shih-Liang Wang, Jonathan Tsung-Yung Chang, Yu-Der Chih, Cheng-En Lee
  • Publication number: 20210175160
    Abstract: A wiring board and a method of manufacturing the same are provided. The method includes the following steps. A substrate is provided. The substrate is perforated to form at least one through hole. A first conductive layer is integrally formed on a surface of the substrate and an inner wall of the through hole. An etch stop layer is formed on a portion of the first conductive layer on the surface of the substrate and another portion of the first conductive layer on the inner wall of the through hole. A second conductive layer is integrally formed on the etch stop layer and the first conductive layer on the inner wall of the through hole. A plug-hole column is formed by filling with a plugged-hole material in the through hole. The second conductive layer is removed. The etch stop layer is then removed.
    Type: Application
    Filed: January 21, 2020
    Publication date: June 10, 2021
    Inventor: Shih-Liang CHENG
  • Publication number: 20200319386
    Abstract: An optical filter and a method for forming the same are provided. The optical filter includes a substrate and a plurality of filter stacks formed on the substrate. Each of the plurality of filter stacks includes a higher-refractive-index layer, a medium-refractive-index layer, and a lower-refractive-index layer. The higher-refractive-index layer has a first refractive index of higher than 3.5. The medium-refractive-index layer is disposed on the higher-refractive-index layer. The medium-refractive-index layer has a second refractive index higher than 2.9 and lower than the first refractive index. The lower-refractive-index layer is disposed on the medium-refractive-index layer. The lower-refractive-index layer has a third refractive index lower than the second refractive index.
    Type: Application
    Filed: April 8, 2019
    Publication date: October 8, 2020
    Inventors: Yu-Jen CHEN, Chung-Hao LIN, Shih-Liang KU