Patents by Inventor Shih-Liang Chou

Shih-Liang Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7867634
    Abstract: A ITO layer structure, which is composed of the ITO as the outermost layer and the first anti-reflected layer on the specific side of the transparent substrate, furthermore, the second anti-reflected layer is formed on the opposite side of substrate, can improve the total transmittance.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: January 11, 2011
    Assignee: Applied Vacuum Coating Technologies Co., Ltd.
    Inventors: Jau-Jier Chu, I-Wen Lee, Shih-Liang Chou, Po-Yao Lai, Chien-Min Weng
  • Publication number: 20110001721
    Abstract: The present invention discloses a touch panel structure formed by an anti-scratch surface layer and a capacitive sensor layer, and a transparent lamination layer is used for pasting the two into a panel. The capacitive sensor layer includes an X-axis first transparent conductive layer and a Y-axis second transparent conductive layer formed on both sides of a transparent plastic carrier to provide a touch panel structure having the advantages of a relatively low material cost, a light weight, an easy manufacturing and molding, a better lamination yield and a flexible and break-free feature.
    Type: Application
    Filed: July 2, 2009
    Publication date: January 6, 2011
    Inventors: Hsueh-Chih Chiang, Shih-Liang Chou, Jyh-An Chen, Ming-Hung Hsieh
  • Publication number: 20100215931
    Abstract: A ITO layer structure, which is composed of the ITO as the outermost layer and the first anti-reflected layer on the specific side of the transparent substrate, furthermore, the second anti-reflected layer is formed on the opposite side of substrate, can improve the total transmittance.
    Type: Application
    Filed: December 10, 2007
    Publication date: August 26, 2010
    Inventors: Jau-Jier Chu, I-Wen Lee, Shih-Liang Chou, Po-Yao Lai, Chien-Min Weng
  • Publication number: 20100214230
    Abstract: A two-stage manufacturing process for preparation of an ITO layer includes having first a transparent substrate, e.g., a glass or plastic substrate going through treatment without preheating; the substrate is then sputtering processed in a sputtering chamber under process conditions without heating up to form a amorphous state ITO film on the surface of the transparent substrate; followed with a thermal treatment at a preset temperature to turn the ITO layer into a crystalline state without compromising strength of the glass or the plastic substrate while delivering a durable ITO layer and a structure of ITO layer provided with a specific sheet resistance and/or thickness. The ITO layer produced using the present invention particularly fits to be applied in a touch screen structure.
    Type: Application
    Filed: October 30, 2007
    Publication date: August 26, 2010
    Inventors: Jau-Jier Chu, I-Wen Lee, Shih-Liang Chou, Po-Yao Lai, Chien-Min Weng
  • Publication number: 20100154878
    Abstract: The electrode according to the invention comprises a substrate, an indium tin oxide film and a semiconductor layer and is produced under a processing condition that the substrate is subjected to ITO sputtering in a sputter chamber at a temperature of less than 200° C., preferably without being treated with heat, and then undergoes a high temperature treatment so as to form a stable ITO film. By this way, a semiconductor layer could be also formed on the indium tin oxide film. The electrode structure so produced is resistant to high temperature and has a reduced resistance change ratio. The electrode structure is especially suited for being used in a dye-sensitized solar cell to enhance the photoelectric conversion efficiency thereof.
    Type: Application
    Filed: December 20, 2008
    Publication date: June 24, 2010
    Inventors: JYH-AN CHEN, SHIH-LIANG CHOU
  • Publication number: 20100101937
    Abstract: A method of fabricating transparent conductive film including the following steps is provided. First, a reactive chamber having at least a target and at least a heating device is provided. Subsequentially, a plasma is generated in the reactive chamber, wherein the plasma is located above the target. Next, the plasma is heated by the heating device from a standby temperature to a working temperature. Simultaneously, a hard plastic substrate is passed above the plasma at a specific speed, wherein the particles of the target are bombarded by the plasma so as to form transparent conductive film on the hard plastic substrate.
    Type: Application
    Filed: October 29, 2008
    Publication date: April 29, 2010
    Applicant: Applied Vacuum Coating Technologies Co., Ltd.
    Inventors: Chien-Min Weng, Tzu-Wen Chu, Chiao-Ning Huang, I-Wen Lee, Shih-Liang Chou
  • Publication number: 20070259190
    Abstract: A method for producing an ITO transparent substrate with a high resistance at a low-temperature sputtering process is provided for mass production. The method is characterized by: a film of ITO mixed with metallic-oxide target and coated with multiple layers provides a transparent capacity. The film can be produced via a production line and further heated and annealed for stabilizing the high resistance thereof.
    Type: Application
    Filed: May 2, 2006
    Publication date: November 8, 2007
    Inventors: Jau-Jier Chu, Chien-Min Weng, Shih-Liang Chou
  • Patent number: 7026171
    Abstract: A rapid thermal annealing (“RTA”) process providing for an RTA equipment is disclosed. The RTA equipment has a pyrometer providing for measuring an operation parameter, e.g., a temperature of the RTA process. The RTA process comprises steps of proceeding a first RTA step to a wafer in the RTA equipment, then comparing a measured value of the operation parameter with a reference range of value of the operation parameter, thereafter proceeding a second RTA step to the wafer in the RTA equipment when the measured value of the operation parameter is in between the reference range of value of the operation parameter. When the measured value of the operation parameter is out of the reference range of value of the operation parameter, the RTA equipment is turned off, and the wafer is unloaded from the RTA equipment and loaded into another RTA equipment to complete the RTA process.
    Type: Grant
    Filed: July 4, 2003
    Date of Patent: April 11, 2006
    Assignee: Macronix International Co., Ltd.
    Inventors: Y. Y. Chang, Shih-Liang Chou, L. H. Lee, Tsung-De Lin, Kou-Yow Tseng, Wen-Cheng Lien
  • Patent number: 6916736
    Abstract: A method of forming an intermetal dielectric (IMD) layer. At least one metal wire is formed on a substrate. A filling oxide layer is formed on the substrate and the metal wire. The surface of the filling oxide layer is smoothed. A first silicon-rich oxide layer is formed on the filling oxide layer, where the refractive index (RI) of the first silicon-rich oxide layer is 1.6˜1.64. A second silicon-rich oxide layer is formed on the first silicon-rich oxide layer, where the refractive index of the second silicon-rich oxide layer is 1.49˜1.55. According to the present method, the diffusion of mobile hydrogen ions is blocked by manufacture with dual silicon-rich oxide layers.
    Type: Grant
    Filed: March 19, 2003
    Date of Patent: July 12, 2005
    Assignee: Macronix International Co., Ltd.
    Inventors: Fu-Hsiang Hsu, U-Way Tseng, Hung-Yu Chiu, Shih-Liang Chou, Shin-Yi Chou
  • Patent number: 6828208
    Abstract: A method of fabricating a shallow trench isolation (STI) structure. A substrate is provided and then a pad oxide layer, a mask layer and a first trench are sequentially formed on the substrate. An insulation layer is formed inside the first trench and over the substrate. The insulation layer has a second trench in a location above the first trench. Thereafter, a conformal cap layer is formed over the insulation layer. The cap layer has a third trench in a location above the second trench. A reverse mask is formed over the cap layer covering the third trench. The cap layer and the insulation layer outside the reverse mask are removed to expose the upper surface of the mask layer. The reverse mask is removed and then the residual insulation layer outside the remaining cap layer and the trench are moved to expose the upper surface of the mask layer. Finally, the mask layer and the pad oxide layer are removed.
    Type: Grant
    Filed: January 28, 2003
    Date of Patent: December 7, 2004
    Assignee: Macronix International Co., Ltd.
    Inventors: Tsung-De Lin, Hsiao-Kang Wang, Tian-Jue Hong, Shih-Liang Chou, Wen-Cheng Lien
  • Publication number: 20040224538
    Abstract: A rapid thermal annealing (“RTA”) process providing for an RTA equipment is disclosed. The RTA equipment has a pyrometer providing for measuring an operation parameter, e.g., a temperature of the RTA process. The RTA process comprises steps of proceeding a first RTA step to a wafer in the RTA equipment, then comparing a measured value of the operation parameter with a reference range of value of the operation parameter, thereafter proceeding a second RTA step to the wafer in the RTA equipment when the measured value of the operation parameter is in between the reference range of value of the operation parameter. When the measured value of the operation parameter is out of the reference range of value of the operation parameter, the RTA equipment is turned off, and the wafer is unloaded from the RTA equipment and loaded into another RTA equipment to complete the RTA process.
    Type: Application
    Filed: July 4, 2003
    Publication date: November 11, 2004
    Inventors: Y. Y. Chang, Shih-Liang Chou, L. H. Lee, Tsung-De Lin, Kou-Yow Tseng, Wen-Cheng Lien
  • Publication number: 20040147135
    Abstract: A method of fabricating a shallow trench isolation (STI) structure. A substrate is provided and then a pad oxide layer, a mask layer and a first trench are sequentially formed on the substrate. An insulation layer is formed inside the first trench and over the substrate. The insulation layer has a second trench in a location above the first trench. Thereafter, a conformal cap layer is formed over the insulation layer. The cap layer has a third trench in a location above the second trench. A reverse mask is formed over the cap layer covering the third trench. The cap layer and the insulation layer outside the reverse mask are removed to expose the upper surface of the mask layer. The reverse mask is removed and then the residual insulation layer outside the remaining cap layer and the trench are moved to expose the upper surface of the mask layer. Finally, the mask layer and the pad oxide layer are removed.
    Type: Application
    Filed: January 28, 2003
    Publication date: July 29, 2004
    Inventors: Tsung-De Lin, Hsiao-Kang Wang, Tian-Jue Hong, Shih-Liang Chou, Wen-Cheng Lien
  • Publication number: 20040146643
    Abstract: A method of determining the deposition temperature, especially inside the reaction chamber of a chemical vapor deposition station. The method includes placing a deposition substrate inside the reaction chamber, forming a layer of metal silicide over the deposition substrate, measuring the silicon/metal atomic ratio and finding the deposition temperature according to a pre-determined temperature versus silicon/metal atomic ratio relationship. The method permits immediate determination as well as real-time monitoring of deposition temperature inside the station.
    Type: Application
    Filed: January 24, 2003
    Publication date: July 29, 2004
    Inventors: Shih-Liang Chou, Tsung-Chin Wu, Tsung-De Lin, Tian-Jue Hong, Kou-Yow Tseng, Wen-Cheng Lien
  • Publication number: 20030181030
    Abstract: A method of forming an intermetal dielectric (IMD) layer. At least one metal wire is formed on a substrate. A filling oxide layer is formed on the substrate and the metal wire. The surface of the filling oxide layer is smoothed. A first silicon-rich oxide layer is formed on the filling oxide layer, where the refractive index (RI) of the first silicon-rich oxide layer is 1.6˜1.64. A second silicon-rich oxide layer is formed on the first silicon-rich oxide layer, where the refractive index of the second silicon-rich oxide layer is 1.49˜1.55. According to the present method, the diffusion of mobile hydrogen ions is blocked by manufacture with dual silicon-rich oxide layers.
    Type: Application
    Filed: March 19, 2003
    Publication date: September 25, 2003
    Inventors: Fu-Hsiang Hsu, U-Way Tseng, Hung-Yu Chiu, Shih-Liang Chou, Shin-Yi Chou
  • Publication number: 20030131394
    Abstract: A stretch garment for body slimming and health caring is made of fabric with good-stretch, light, thin, good-strength special treatment to help people healthy. The fabric comprises a skin layer, a middle layer and an inner layer. The skin layer is made of polyurethane (PU), thermal polyurethane (TPU) or artificial leather. The middle layer could be added the powder of far-infrared ray, curing of perfume and the oils of aromatherapy, anti-bacteria, herbs, medicines or the formula of negative ion to reduce people stress, and so on. The inner layer is made of warm-fiber fabric. Due to the combination, fats in a human body could be burn easily during exercise and the specific formula in the fabric could be absorbed through the skin or taking breath so that the garment could not only make people slim but also keep people's bodies health.
    Type: Application
    Filed: December 27, 2001
    Publication date: July 17, 2003
    Inventor: Shih-Liang Chou
  • Publication number: 20030111337
    Abstract: An apparatus and a method for monitoring the ion concentration in an etching chamber of a sputter etch process are described, wherein the DC bias of a pre-clean process for a sputter etch process is acquired. The parameters of the pre-clean process for the sputter etch process are then adjusted according to the value of the monitored DC bias. The DC bias thus varies within a certain range to provide a steady control of the ion concentration and to reduce the defects formed in the wafer.
    Type: Application
    Filed: April 3, 2002
    Publication date: June 19, 2003
    Inventors: Chien-Chia Lin, Shih-Liang Chou, Kuo-Wei Shyu