Patents by Inventor Shih-Liang Wang

Shih-Liang Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240348435
    Abstract: Systems and methods of generating a security key for an integrated circuit device include generating a plurality of key bits with a physically unclonable function (PUF) device. The PUF can include a random number generator that can create random bits. The random bits may be stored in a nonvolatile memory. The number of random bits stored in the nonvolatile memory allows for a plurality of challenge and response interactions to obtain a plurality of security keys from the PUF.
    Type: Application
    Filed: April 2, 2024
    Publication date: October 17, 2024
    Inventors: Shih-Lien Linus Lu, Kun-hsi Li, Shih-Liang Wang, Jonathan Tsung-Yung Chang, Yu-Der Chih, Cheng-En Lee
  • Patent number: 11962693
    Abstract: Systems and methods of generating a security key for an integrated circuit device include generating a plurality of key bits with a physically unclonable function (PUF) device. The PUF can include a random number generator that can create random bits. The random bits may be stored in a nonvolatile memory. The number of random bits stored in the nonvolatile memory allows for a plurality of challenge and response interactions to obtain a plurality of security keys from the PUF.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Lien Linus Lu, Kun-hsi Li, Shih-Liang Wang, Jonathan Tsung-Yung Chang, Yu-Der Chih, Cheng-En Lee
  • Publication number: 20230121502
    Abstract: Systems and methods of generating a security key for an integrated circuit device include generating a plurality of key bits with a physically unclonable function (PUF) device. The PUF can include a random number generator that can create random bits. The random bits may be stored in a nonvolatile memory. The number of random bits stored in the nonvolatile memory allows for a plurality of challenge and response interactions to obtain a plurality of security keys from the PUF.
    Type: Application
    Filed: December 9, 2022
    Publication date: April 20, 2023
    Inventors: Shih-Lien Linus Lu, Kun-hsi Li, Shih-Liang Wang, Jonathan Tsung-Yung Chang, Yu-Der Chih, Cheng-En Lee
  • Patent number: 11528135
    Abstract: Systems and methods of generating a security key for an integrated circuit device include generating a plurality of key bits with a physically unclonable function (PUF) device. The PUF can include a random number generator that can create random bits. The random bits may be stored in a nonvolatile memory. The number of random bits stored in the nonvolatile memory allows for a plurality of challenge and response interactions to obtain a plurality of security keys from the PUF.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: December 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Lien Linus Lu, Kun-hsi Li, Shih-Liang Wang, Jonathan Tsung-Yung Chang, Yu-Der Chih, Cheng-En Lee
  • Publication number: 20210306148
    Abstract: Systems and methods of generating a security key for an integrated circuit device include generating a plurality of key bits with a physically unclonable function (PUF) device. The PUF can include a random number generator that can create random bits. The random bits may be stored in a nonvolatile memory. The number of random bits stored in the nonvolatile memory allows for a plurality of challenge and response interactions to obtain a plurality of security keys from the PUF.
    Type: Application
    Filed: November 30, 2020
    Publication date: September 30, 2021
    Inventors: Shih-Lien Linus Lu, Kun-hsi Li, Shih-Liang Wang, Jonathan Tsung-Yung Chang, Yu-Der Chih, Cheng-En Lee
  • Patent number: 6815971
    Abstract: A method and apparatus is provided for stress testing integrated circuits to determine their susceptibility to hot carrier charge injection damage. The system includes a hot carrier injection source formed on a semiconductor wafer carrying the ICs under test. The carrier source comprises an adjustable, voltage controlled oscillator having a variable frequency AC output test signal, and a modulator circuit for varying the duty cycle of the test signal applied to the ICs.
    Type: Grant
    Filed: November 6, 2002
    Date of Patent: November 9, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Chien-Jung Wang, Shih-Liang Wang, Chao-Hao Cheng
  • Publication number: 20040085084
    Abstract: A method and apparatus is provided for stress testing integrated circuits to determine their susceptibility to hot carrier charge injection damage. The system includes a hot carrier injection source formed on a semiconductor wafer carrying the ICs under test. The carrier source comprises an adjustable, voltage controlled oscillator having a variable frequency AC output test signal, and a modulator circuit for varying the duty cycle of the test signal applied to the ICs.
    Type: Application
    Filed: November 6, 2002
    Publication date: May 6, 2004
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Jung Wang, Shih-Liang Wang, Chao-Hao Cheng