Abstract: A method of forming a MEM device with an integrated circuit that includes providing a semiconductor substrate including a first region and a second region, forming an integrated circuit device on the first region, forming a first insulating layer on the semiconductor substrate, etching the first insulating layer to form a first dielectric layer on the first region and a second dielectric layer on the second region spaced apart from the first dielectric layer, forming a second insulating layer over the semiconductor substrate, the first dielectric layer and the second dielectric layer, etching the second insulating layer to expose the first dielectric layer, forming a third insulating layer over the semiconductor substrate, the second insulatng layer and the first dielectric layer, etching the third insulating layer to form a plurality of vias, and forming a metal layer over the semiconductor substrate to fill the vias.

Abstract: A method of fabricating a semiconductor memory device, particularly a mask ROM. A sacrificial oxide layer is formed on a silicon substrate and then a photoresist layer is formed on the sacrificial oxide layer. The photoresist layer is patterned to form a plurality of openings where bit lines are to extend respectively. Taking the patterned photoresist layer as a mask, arsenic ions are implanted into the silicon substrate through the openings and then boron ions are implanted into the silicon substrate through the openings. The implantation depth of boron ions are deeper than arsenic ions. The photoresist layer and the sacrificial oxide layer are removed after implantation. A gate oxide and a field oxide are grown simultaneously on the non-implanted and the implanted regions of the semiconductor layers respectively and a gate conductive layer is deposited on the silicon substrate.

Abstract: A semiconductor device having a memory array that includes a plurality of substantially parallel word lines, a plurality of substantially parallel bit lines, wherein each of the plurality of the word lines is substantially perpendicular to each of the plurality of the bit lines, a first dummy word line disposed at a periphery of the memory array, wherein the first dummy word line is substantially parallel to the plurality of word lines and overlaps at least two non-adjacent bit lines.

Abstract: A semiconductor device having a memory array that includes a plurality of substantially parallel word lines, a plurality of substantially parallel bit lines, wherein each of the plurality of the word lines is substantially perpendicular to each of the plurality of the bit lines, a first dummy word line disposed at a periphery of the memory array, wherein the first dummy word line is substantially parallel to the plurality of word lines and overlaps at least two non-adjacent bit lines.

Abstract: A semiconductor device having a memory array that includes a plurality of substantially parallel word lines, a plurality of substantially parallel bit lines, wherein each of the plurality of the word lines is substantially perpendicular to each of the plurality of the bit lines, a first dummy word line disposed at a periphery of the memory array, wherein the first dummy word line is substantially parallel to the plurality of word lines and overlaps at least two non-adjacent bit lines.

Abstract: A method of fabricating a semiconductor memory device, particularly a mask ROM. A sacrificial oxide layer is formed on a silicon substrate and then a photoresist layer is formed on the sacrificial oxide layer. The photoresist layer is patterned to form a plurality of openings where bit lines are to extend respectively. Taking the patterned photoresist layer as a mask, arsenic ions are implanted into the silicon substrate through the openings and then boron ions are implanted into the silicon substrate through the openings. The implantation depth of boron ions are deeper than arsenic ions. The photoresist layer and the sacrificial oxide layer are removed after implantation. A gate oxide and a field oxide are grown simultaneously on the non-implanted and the implanted regions of the semiconductor layers respectively and a gate conductive layer is deposited on the silicon substrate.