Patents by Inventor Shih-Lu HSU

Shih-Lu HSU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10978462
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack and a conductive layer over a semiconductor substrate. The method includes forming a negative photoresist layer to cover the gate stack and a first portion of the conductive layer over the isolation structure and expose a second portion of the conductive layer. The method includes forming a mask layer over the negative photoresist layer and the conductive layer. The mask layer has trenches over the second portion of the conductive layer and an edge portion of the negative photoresist layer, and a thickness of the edge portion decreases in a direction away from the gate stack.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Yen Hsaio, Cheng-Ming Wu, Shih-Lu Hsu, Chien-Hsian Wang
  • Publication number: 20210043774
    Abstract: A semiconductor device includes a substrate, a tunneling oxide layer, a floating gate, an isolation layer and a control gate. The tunneling oxide layer is over the substrate. The floating gate is over the tunneling oxide layer. The isolation layer covers a top of the floating gate and peripherally encloses the tunneling oxide layer and the floating gate. The control gate is over a top of the isolation layer.
    Type: Application
    Filed: October 23, 2020
    Publication date: February 11, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Lu HSU, Ping-Pang HSIEH, Szu-Hsien LU, Yu-Chu LIN
  • Patent number: 10818804
    Abstract: A semiconductor device includes a substrate, a tunneling oxide layer, a floating gate, an isolation layer and a control gate. The tunneling oxide layer is disposed on the substrate. The floating gate is disposed on the tunneling oxide layer. The isolation layer covers a top of the floating gate and peripherally encloses the tunneling oxide layer and the floating gate. The control gate is disposed over a top of the isolation layer.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Lu Hsu, Ping-Pang Hsieh, Szu-Hsien Lu, Yu-Chu Lin
  • Publication number: 20200058661
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack and a conductive layer over a semiconductor substrate. The method includes forming a negative photoresist layer to cover the gate stack and a first portion of the conductive layer over the isolation structure and expose a second portion of the conductive layer. The method includes forming a mask layer over the negative photoresist layer and the conductive layer. The mask layer has trenches over the second portion of the conductive layer and an edge portion of the negative photoresist layer, and a thickness of the edge portion decreases in a direction away from the gate stack.
    Type: Application
    Filed: October 24, 2019
    Publication date: February 20, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Ching-Yen HSAIO, Cheng-Ming WU, Shih-Lu HSU, Chien-Hsian WANG
  • Patent number: 10461088
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack and a conductive layer over a semiconductor substrate. The semiconductor substrate has a first region and a second region isolated from each other by an isolation structure in the semiconductor substrate. The gate stack is formed over the first region. The method includes forming a negative photoresist layer over the first region and a first portion of the conductive layer over the isolation structure to cover the gate stack. The method includes forming a mask layer over the negative photoresist layer and the conductive layer. The mask layer has trenches over a second portion of the conductive layer. The method includes removing the second portion through the trenches. The method includes removing the mask layer. The method includes removing the negative photoresist layer.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: October 29, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Yen Hsaio, Cheng-Ming Wu, Shih-Lu Hsu, Chien-Hsian Wang
  • Patent number: 10283604
    Abstract: A method of fabricating semiconductor device includes forming a plurality of gate structures on a semiconductor substrate. A first inter layer dielectric layer is deposited on the gate structures. A first contact plug is formed in the first inter layer dielectric layer in between every two immediately adjacent gate structures. An etch stop layer is deposited on the first inter layer dielectric layer. A second inter layer dielectric layer is deposited on the first inter layer dielectric layer. A second contact plug is formed in the second inter layer dielectric layer aligning with the first contact plug. A metal layer is deposited overlying the second inter layer dielectric layer and the second contact plug.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Szu-Hsien Lu, Hung-Che Liao, Kun-Tsang Chuang, Shih-Lu Hsu, Yu-Chu Lin, Jyun-Guan Jhou
  • Patent number: 10141401
    Abstract: A method for forming a semiconductor device structure is provided. The method includes performing a first plasma etching process on a substrate to form a first trench in the substrate. The method includes removing a second portion of the substrate under the bottom surface to form a second trench under and connected to the first trench. The second trench surrounds a third portion of the substrate under the first portion. The third portion has a first sidewall. The first sidewall is inclined relative to the top surface at a second angle, and the first angle is greater than the second angle. The method includes forming an isolation structure in the first trench and the second trench. The method includes forming a gate insulating layer over the top surface and the first inclined surface. The method includes forming a gate over the gate insulating layer and the isolation structure.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: November 27, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Lu Hsu, Ping-Pang Hsieh, Yu-Chu Lin, Jyun-Guan Jhou
  • Publication number: 20180226419
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack and a conductive layer over a semiconductor substrate. The semiconductor substrate has a first region and a second region isolated from each other by an isolation structure in the semiconductor substrate. The gate stack is formed over the first region. The method includes forming a negative photoresist layer over the first region and a first portion of the conductive layer over the isolation structure to cover the gate stack. The method includes forming a mask layer over the negative photoresist layer and the conductive layer. The mask layer has trenches over a second portion of the conductive layer. The method includes removing the second portion through the trenches. The method includes removing the mask layer. The method includes removing the negative photoresist layer.
    Type: Application
    Filed: March 30, 2018
    Publication date: August 9, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Ching-Yen HSAIO, Cheng-Ming WU, Shih-Lu HSU, Chien-Hsian WANG
  • Patent number: 9941294
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first gate stack over the semiconductor substrate. The first gate stack includes a first gate and a second gate over the first gate, and the first gate and the second gate are electrically isolated from each other. The semiconductor device structure includes a ring structure surrounding the first gate stack. The ring structure is made of a conductive material.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: April 10, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ching-Yen Hsaio, Cheng-Ming Wu, Shih-Lu Hsu, Chien-Hsian Wang
  • Patent number: 9825046
    Abstract: A flash memory cell structure includes a semiconductor substrate, a pad dielectric layer, a floating gate, a control gate, and a blocking layer. The pad dielectric layer is disposed on the semiconductor substrate. The floating gate is disposed over the pad dielectric layer, in which the floating gate has a top surface opposite to the pad dielectric layer, and the top surface includes at least one recess formed thereon. The control gate is disposed over the top surface of the floating gate. The blocking layer is disposed between the floating gate and the control gate.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: November 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chu Lin, Hung-Che Liao, Kun-Tsang Chuang, Shih-Lu Hsu
  • Publication number: 20170263464
    Abstract: A method for forming a semiconductor device structure is provided. The method includes performing a first plasma etching process on a substrate to form a first trench in the substrate. The method includes removing a second portion of the substrate under the bottom surface to form a second trench under and connected to the first trench. The second trench surrounds a third portion of the substrate under the first portion. The third portion has a first sidewall. The first sidewall is inclined relative to the top surface at a second angle, and the first angle is greater than the second angle. The method includes forming an isolation structure in the first trench and the second trench. The method includes forming a gate insulating layer over the top surface and the first inclined surface. The method includes forming a gate over the gate insulating layer and the isolation structure.
    Type: Application
    Filed: May 26, 2017
    Publication date: September 14, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Lu HSU, Ping-Pang HSIEH, Yu-Chu LIN, Jyun-Guan JHOU
  • Publication number: 20170194336
    Abstract: A flash memory cell structure includes a semiconductor substrate, a pad dielectric layer, a floating gate, a control gate, and a blocking layer. The pad dielectric layer is disposed on the semiconductor substrate. The floating gate is disposed over the pad dielectric layer, in which the floating gate has a top surface opposite to the pad dielectric layer, and the top surface includes at least one recess formed thereon. The control gate is disposed over the top surface of the floating gate. The blocking layer is disposed between the floating gate and the control gate.
    Type: Application
    Filed: January 5, 2016
    Publication date: July 6, 2017
    Inventors: Yu-Chu LIN, Hung-Che LIAO, Kun-Tsang CHUANG, Shih-Lu HSU
  • Patent number: 9666668
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a trench surrounding an active island of the substrate. The active island has a top surface, a sidewall, and an inclined surface connecting the top surface to the sidewall. The inclined surface is inclined relative to the top surface at a first angle. The sidewall is inclined relative to the top surface at a second angle. The first angle is greater than the second angle. The semiconductor device structure includes an isolation structure in the trench. The semiconductor device structure includes a gate insulating layer over the top surface and the inclined surface. The semiconductor device structure includes a gate over the gate insulating layer and the isolation structure. The gate crosses the active island.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: May 30, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Lu Hsu, Ping-Pang Hsieh, Yu-Chu Lin, Jyun-Guan Jhou
  • Publication number: 20170125602
    Abstract: A semiconductor device includes a substrate, a tunneling oxide layer, a floating gate, an isolation layer and a control gate. The tunneling oxide layer is disposed on the substrate. The floating gate is disposed on the tunneling oxide layer. The isolation layer covers a top of the floating gate and peripherally encloses the tunneling oxide layer and the floating gate. The control gate is disposed over a top of the isolation layer.
    Type: Application
    Filed: October 28, 2015
    Publication date: May 4, 2017
    Inventors: Shih-Lu HSU, Ping-Pang HSIEH, Szu-Hsien LU, Yu-Chu LIN
  • Publication number: 20170117355
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a trench surrounding an active island of the substrate. The active island has a top surface, a sidewall, and an inclined surface connecting the top surface to the sidewall. The inclined surface is inclined relative to the top surface at a first angle. The sidewall is inclined relative to the top surface at a second angle. The first angle is greater than the second angle. The semiconductor device structure includes an isolation structure in the trench. The semiconductor device structure includes a gate insulating layer over the top surface and the inclined surface. The semiconductor device structure includes a gate over the gate insulating layer and the isolation structure. The gate crosses the active island.
    Type: Application
    Filed: October 27, 2015
    Publication date: April 27, 2017
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Lu HSU, Ping-Pang HSIEH, Yu-Chu LIN, Jyun-Guan JHOU
  • Publication number: 20170053928
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first gate stack over the semiconductor substrate. The first gate stack includes a first gate and a second gate over the first gate, and the first gate and the second gate are electrically isolated from each other. The semiconductor device structure includes a ring structure surrounding the first gate stack. The ring structure is made of a conductive material.
    Type: Application
    Filed: August 21, 2015
    Publication date: February 23, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ching-Yen HSAIO, Cheng-Ming WU, Shih-Lu HSU, Chien-Hsian WANG
  • Publication number: 20170033047
    Abstract: A method of fabricating semiconductor device includes forming a plurality of gate structures on a semiconductor substrate. A fist inter layer dielectric layer is deposited on the gate structures. A first contact plug is formed in the first inter layer dielectric layer in between every two immediately adjacent gate structures. An etch stop layer is deposited on the first inter layer dielectric layer. A second inter layer dielectric layer is deposited on the first inter layer dielectric layer. A second contact plug is formed in the second inter layer dielectric layer aligning with the first contact plug. A metal layer is deposited overlying the second inter layer dielectric layer and the second contact plug.
    Type: Application
    Filed: July 31, 2015
    Publication date: February 2, 2017
    Inventors: Szu-Hsien LU, Hung-Che LIAO, Kun-Tsang CHUANG, Shih-Lu HSU, Yu-Chu LIN, Jyun-Guan JHOU