Abstract: An organic electroluminescent display panel, a fabrication method thereof, and a display device are provided. The organic electroluminescent display panel includes: a base substrate and a package cover plate disposed opposite to each other, and an organic electroluminescent structure disposed on the base substrate and provided between the base substrate and the package cover plate. The package cover plate has a first groove for accommodating the organic electroluminescent structure within a display region of the organic electroluminescent display panel; the package cover plate has at least one second groove surrounding the first groove and having a closed boundary within a non-display region of the organic electroluminescent display panel; the second groove accommodates a sealant; and a metal layer is located between a protrusion portion of the package cover plate and the base substrate.

Abstract: An organic electroluminescent display panel, a fabrication method thereof, and a display device are provided. The organic electroluminescent display panel comprises: a base substrate and a package cover plate disposed opposite to each other, and an organic electroluminescent structure disposed on the base substrate and provided between the base substrate and the package cover plate. The package cover plate has a first groove for accommodating the organic electroluminescent structure within a display region of the organic electroluminescent display panel; the package cover plate has at least one second groove surrounding the first groove and having a closed boundary within a non-display region of the organic electroluminescent display panel; the second groove accommodates a sealant; and there is a metal layer between a protrusion portion of the package cover plate and the base substrate.

Abstract: An organic electroluminescent display panel, a fabrication method thereof, and a display device are provided. The organic electroluminescent display panel comprises: a base substrate and a package cover plate disposed opposite to each other, and an organic electroluminescent structure disposed on the base substrate and provided between the base substrate and the package cover plate. The package cover plate has a first groove for accommodating the organic electroluminescent structure within a display region of the organic electroluminescent display panel; the package cover plate has at least one second groove surrounding the first groove and having a closed boundary within a non-display region of the organic electroluminescent display panel; the second groove accommodates a sealant; and there is a metal layer between a protrusion portion of the package cover plate and the base substrate.

Abstract: An oscillation module includes a frequency generator, a signal calibrator, a multiplexer, and a controller. The oscillation module is calibrated by using calibration parameters and a control instruction of which the frequency and phase are the same as the oscillation frequency signal generated by the frequency generator. As a consequence, an electronic pin used for processing asynchronous signals can be saved so as to reduce the chip area of the oscillation module.

Abstract: An oscillation module includes a frequency generator, a signal calibrator, a multiplexer, and a controller. The oscillation module is calibrated by using calibration parameters and a control instruction of which the frequency and phase are the same as the oscillation frequency signal generated by the frequency generator. As a consequence, an electronic pin used for processing asynchronous signals can be saved so as to reduce the chip area of the oscillation module.

Abstract: The present invention discloses an efficient way to match the impedance between a pull-up path and a pull-down path of an IO cell without using stacked devices on the output stage of the IO cell to save area and to achieve higher speed; back-gate (bulk or body) voltages of a pull-up transistor and a pull-down transistor of the IO cell can be respectively adjusted to a value to achieve the desired impedance values of the pull-up and pull-down paths. A central calibration unit can generate an impedance calibration code and distribute them to a local adjustable bias generator in each IO cell groups, wherein the local adjustable bias generator, which is embedded in a power or a ground pad, receives the impedance calibration code and generates bias voltages to the back-gates of the pull-up and pull-down transistors for setting impedance values of the pull-up and pull-down paths, respectively.

Abstract: The present invention discloses an efficient way to read data from a memory device by aligning an internal clock of the memory interface circuit with the read data strobe signal from the memory device by delaying the internal clock along with control signals for reading the memory device before transmitting them to the memory device, wherein the internal clock of the memory controller can sample the read data from the memory device directly without using a FIFO device between the internal clock and the read data strobe so as to reduce latency of reading data from the memory device. For example, the memory device can be a double-data-rate (DDR) DRAM device, and the control signals includes command and address signals of the DDR DRAM device.

Abstract: A signal delay circuit comprising: a first delay stage, for delaying a first input signal to generate a first delay signal; and a second delay stage, for cooperating with part of delay units of the first delay stage to delay the first delay signal to generate a second delay signal. The signal delay circuit selectively enables the delay stages of the first delay stage or the second delay stage, wherein the signal delay circuit mixes the first delay signal and the second delay signal to generate a first mixed signal when the first delay stage and the second delay stage are both enabled.

Abstract: The invention provides an electronic device for reducing simultaneous switching noise (SSN). The electronic device includes: a driver, driving an external device according to an input signal, and including: an input end, receiving the input signal; a positive output end, coupled to an external capacitor of the external device; and a negative output end, coupled to a variable capacitor; and a loading calibration circuit, generating an adjusting signal to adjust a first capacitance of the variable capacitor so as to make the first capacitance approximately equal to a second capacitance of the external capacitor.

Abstract: A signal delay circuit comprising: a first delay stage, for delaying a first input signal to generate a first delay signal; and a second delay stage, for cooperating with part of delay units of the first delay stage to delay the first delay signal to generate a second delay signal. The signal delay circuit selectively enables the delay stages of the first delay stage or the second delay stage, wherein the signal delay circuit mixes the first delay signal and the second delay signal to generate a first mixed signal when the first delay stage and the second delay stage are both enabled.

Abstract: The invention provides an electronic device for reducing simultaneous switching noise (SSN). The electronic device includes: a driver, driving an external device according to an input signal, and including: an input end, receiving the input signal; a positive output end, coupled to an external capacitor of the external device; and a negative output end, coupled to a variable capacitor; and a loading calibration circuit, generating an adjusting signal to adjust a first capacitance of the variable capacitor so as to make the first capacitance approximately equal to a second capacitance of the external capacitor.

Abstract: A delay locked loop (DLL) circuit for improving jitters includes a detecting unit, a master controller, a slave controller, first and second variable delay lines, first and second dummy loads, and a processor. The master controller generates a first control signal in response to a detecting signal. The slave controller generates a second control signal in response to the detecting signal. The first variable delay line delays a reference clock in response to the first control signal so as to generate a delay clock. The processor is configured to selectively generate a slave input signal, wherein if the processor does not generate the slave input signal, the processor makes the second dummy load draw a load current from the slave controller.

Abstract: A three-dimensional SoC structure formed by stacking multiple chip modules is provided. The three-dimensional SoC structure includes at least two vertical SoC modules and at least one connector module, wherein each connector module electrically connects two vertical SoC modules. Each vertical SoC module is constructed by stacking at least two chip modules vertically. Each chip module includes a module circuit board and at least one preset element. A recess is formed in each module circuit board and provided with a first connecting interface for electrically connecting with the corresponding at least one preset element. The at least two vertical SoC modules are connected by the connector module to form a three-dimensional SoC structure with multiple functions. Besides, the recesses formed in the module circuit boards provide effective heat dissipation paths for the preset elements.

Abstract: A multi-layer system-on-chip (SoC) module structure is provided. The multi-layer SoC module structure includes at least two circuit board module layers and at least one connector module layer. Each connector module layer is sandwiched between and thus electrically connects two circuit board module layers such that the SoC module structure is formed by stacking. Each circuit board module layer is composed of at least one circuit board module while each connector module layer is composed of at least one connector module. Hence, the SoC module structure can be manufactured as a three-dimensional structure, thus allowing highly flexible connections within the SoC module structure.

Abstract: A socket structure stack and a socket structure thereof are provided. The socket structure stack includes at least two socket structures, and each socket structure includes a main body, a plurality of conductive elements, and a plurality of connecting elements. The main body includes an inner plate and an outer plate, wherein the inner plate has a receiving portion and an embedded portion. The conductive elements are embedded in the embedded portion, and the connecting elements are mounted on the outer plate so as to connect adjacent socket structures together. The socket structures are so configured that ICs, processors, and printed circuit boards connected to the socket structures or the socket structures themselves can be recycled. Moreover, the printed circuit boards can be easily assembled to the socket structures, and the socket structures can be stacked up and securely connected to form a 3D structure which is otherwise difficult to put together by soldering.

Abstract: A three-dimensional SoC structure formed by stacking multiple chip modules is provided. The three-dimensional SoC structure includes at least two vertical SoC modules and at least one connector module, wherein each connector module electrically connects two vertical SoC modules. Each vertical SoC module is constructed by stacking at least two chip modules vertically. Each chip module includes a module circuit board and at least one preset element. A recess is formed in each module circuit board and provided with a first connecting interface for electrically connecting with the corresponding at least one preset element. The at least two vertical SoC modules are connected by the connector module to form a three-dimensional SoC structure with multiple functions. Besides, the recesses formed in the module circuit boards provide effective heat dissipation paths for the preset elements.

Abstract: The present invention discloses a unitized charging and discharging battery management system and a programmable battery management module thereof The unitized charging and discharging battery management system includes a smart battery module and a programmable battery management module, which has a universal loop and a control unit. The smart battery module has at least two smart batteries which are electrically connected by a plurality of switches and circuits of the universal loop to form a charging/discharging loop in series/parallel. The control unit monitors the charging and discharging status of the smart batteries to turn on or off the switches accordingly, so as to manage the smart batteries, thereby enhancing the overall power efficacy of the smart battery module. Besides, the service life of the smart battery module is also prolonged due to the simultaneous charging and discharging capability.

Abstract: A multi-layer system-on-chip (SoC) module structure is provided. The multi-layer SoC module structure includes at least two circuit board module layers and at least one connector module layer. Each connector module layer is sandwiched between and thus electrically connects two circuit board module layers such that the SoC module structure is formed by stacking. Each circuit board module layer is composed of at least one circuit board module while each connector module layer is composed of at least one connector module. Hence, the SoC module structure can be manufactured as a three-dimensional structure, thus allowing highly flexible connections within the SoC module structure.

Abstract: A fabrication method for a system-on-chip (SoC) module is provided. The fabrication method includes the steps of providing at least two SoC sub-modules and connecting the SoC sub-modules. The SoC sub-modules are electrically connected with each other by connection interfaces of the SoC sub-modules so as to form the SoC module. As the SoC sub-modules have been verified in advance, the time required for verifying the resulting SoC module can be significantly reduced. As for application-specific SoC modules, they are fabricated by connecting with application-specific SoC sub-modules via the appropriate connection interfaces. Thus, the time and costs for developing SoC modules can both be minimized.

Abstract: A mixed-voltage input/output buffer having low-voltage design comprises a pre-driver, a tracking unit, a driving unit, and input/output pad, a floating-well unit and a transporting unit. The pre-driver receives first data signal and enable signal and outputs first and second data voltages. The tracking unit provides Gate-Tracking function. The driving unit couples the pre-driver and the tracking unit for production of a first buffer voltage corresponding to the first data voltage. The input/output pad couples the driving unit to output a first buffer voltage and to receive a second data signal. The output unit is used for outputting a second buffer voltage corresponding to the second data signal. The floating-well unit couples to the driving unit and the input/output pad in order to output first buffer voltage and receive second data signal. The floating-well unit is used for preventing leakage current.