Abstract: A light emission apparatus includes a laser diode configured to emit a light; a laser driver electrically coupled to the laser diode, the laser driver being configured to drive the laser diode to generate the light; and an optical module arranged to receive the light emitted by the laser diode, the optical module comprising at least one optical element and being configured to adjust the light and emits a transmitting light; wherein the transmitting light emits from the optical module with an illumination angle and the optical module adjusts the light to vary the illumination angle.

Abstract: An actuating and sensing module is disclosed and includes a bottom plate, a gas pressure sensor, a thin gas transportation device and a cover plate. The bottom plate includes a pressure relief orifice, a discharging orifice and a communication orifice. The gas pressure sensor is disposed on the bottom plate and seals the communication orifice. The thin gas transportation device is disposed on the bottom plate and seals the pressure relief orifice and the discharging orifice. The cover plate is disposed on the bottom plate and covers the gas pressure sensor and the thin gas-transportation device. The cover plate includes an intake orifice. The thin gas transportation device is driven to inhale gas through the intake orifice, the gas is then discharged through the discharging orifice by the thin gas transportation device, and a pressure change of the gas is sensed by the gas pressure sensor.

Abstract: An electronic device and a method for detecting abnormal device operation are provided. The method includes: obtaining multiple action events of a movable input device, and each action event including a relative coordinate and a time stamp of the movable input device; generating multiple absolute coordinates based on the relative coordinate of each action event; estimating multiple speed vectors based on the absolute coordinates and the time stamp of each action event; estimating multiple acceleration vectors based on the speed vectors and the time stamp of each action event; and estimating a probability of abnormal operation based on the speed vectors and the acceleration vectors.

Abstract: In an embodiment, a chemical mechanical planarization (CMP) system includes: a monolithic platen within a platen housing, wherein the monolithic platen is formed of a single piece of material, wherein the monolithic platen includes: a first portion within a first opening, and a second portion within a second opening, wherein the first portion has a different diameter than the second portion; and a polishing fluid delivery module above the monolithic platen, wherein the polishing fluid delivery module is configured to deliver slurry to the monolithic platen during performance of CMP.

Abstract: An oxide spacer for stack DRAM gate stack is described, including: a semiconductor substrate with a memory array region and a periphery region, a plurality of gates disposed within the memory array region and the periphery region respectively, a silicon oxide spacer disposed on the gates, where the polysilicon contact plugs are formed by polysilicon deposition and chemical mechanical polish. After polysilicon contact plugs are formed, a silicon oxide layer is deposited to isolate the contacts and gate. The silicon oxide layer on top of contact plug is removed by chemical mechanical polish achieve planarization.

Abstract: A risk assessment method for process improvement decisions applying for semiconductor process change comprises: performing a risk assessment evaluation to compute a polarity (plurality?) of items corresponding to their values, generating a risk assessment evaluation value to determine if the risk assessment evaluation value is in a risk setting value, go to next two steps; not, go to next step; performing an active inspect for the polarity (plurality?) of items corresponding to their item setting values, if not satisfied with the active inspect, repeat the above step; if not, transferring the semiconductor process change to online process.

Abstract: A display panel including a pixel array region. The pixel array region includes a plurality of pixel cells disposed in a matrix configuration. Each pixel cell has an active device. A relative position of a first active device in a first pixel cell among the pixel cells is different from that of a second active device in a second pixel cell among the pixel cells.

Abstract: A display panel including a pixel array region. The pixel array region includes a plurality of pixel cells disposed in a matrix configuration. Each pixel cell has an active device. A relative position of a first active device in a first pixel cell among the pixel cells is different from that of a second active device in a second pixel cell among the pixel cells.

Abstract: A display panel including a pixel array region. The pixel array region includes a plurality of pixel cells disposed in a matrix configuration. Each pixel cell has an active device. A relative position of a first active device in a first pixel cell among the pixel cells is different from that of a second active device in a second pixel cell among the pixel cells.

Abstract: A heat dissipating system of a high-speed circular knitting machine includes a super low temperature air gun. Cold air is ejected from a cold air outlet of the super low temperature air gun for carrying away the high heat produced by a cylinder base during a knitting process. The super low temperature air gun is connected to an extension pipe and extended to a gap between a cutting disc and a pressing plate, or saddle bases, or a lower rhombus ring and two saddle bases, or yarn feeding nozzles. Cold air ejected from the cold air outlet passes through the gap to the cylinder base or other peripheral components of the high-speed circular knitting machine to achieve the heat dissipating effect. The super low temperature air gun is installed inside a leg for supporting a yarn supplying device or on its external surface or on a yarn feeding ring.

Abstract: A fiber blowing and heat dissipating system of single-sided circular knitting machine includes a fixed rod, a revolving supply device, and a fiber blowing device, wherein the revolving supply device includes a fixed rod, a rotary air supply section, and a driving motor. The fixed axle has an air inlet at its top, and the rotary air supply section has an air passage interconnected with the air inlet and connected to the fiber blowing device, such that the driving motor is driven to rotate around the fixed axle to centralize the air flow to blow away the cotton fibers easily produced at a yarn passing eyelet of the yarn passing plate and the yarn feeding eyelet of a yarn feeding nozzle and a knitting needle. The invention also can lower the heat produced by the friction between the rotation of the needle cylinder and the knitting needle.

Abstract: A method for manufacturing a trench capacitor that includes providing a semiconductor substrate, forming a deep trench in the substrate, forming a thin sacrificial layer on a surface of the trench, and forming a hemispherical silicon grain layer over the thin sacrificial layer, wherein the sacrificial layer has a thickness to act as an etch stop during a subsequent step to remove at least a portion of the hemispherical silicon grain layer, and is electrically conductive.

Abstract: A method for forming a volatile memory structure. A buried trench capacitor in each of a pair of neighboring trenches formed in a substrate. An asymmetric collar insulating layer is formed over an upper portion of the sidewall of each trench and has a high and a low level portions. A conductive layer is formed overlying the buried trench capacitor and below the surface of the substrate. The high level portion is adjacent to the substrate between the neighboring trenches and the low level portion is covered by the conductive layer. A dielectric layer is formed overlying the conductive layer. Two access transistors are formed on the substrate outside of the pair of the neighboring trenches, respectively, which have source/drain regions electrically connecting to the conductive layer. A volatile memory structure is also disclosed.

Abstract: A display panel including a pixel array region. The pixel array region includes a plurality of pixel cells disposed in a matrix configuration. Each pixel cell has an active device. A relative position of a first active device in a first pixel cell among the pixel cells is different from that of a second active device in a second pixel cell among the pixel cells.

Abstract: A dynamic random access memory (DRAM) structure and a fabricating process thereof are provided. In the fabricating process, a channel region is formed with a doped region having identical conductivity as the substrate in a section adjacent to an isolation structure. The doped region is formed in a self-aligned process by conducting a tilt implantation implanting ions into the substrate through the upper portion of the capacitor trench adjacent to the channel region after forming the trench but before the definition of the active region.

Abstract: A method for manufacturing a trench capacitor that includes providing a semiconductor substrate, forming a deep trench in the substrate, forming a thin sacrificial layer on a surface of the trench, and forming a hemispherical silicon grain layer over the thin sacrificial layer, wherein the sacrificial layer has a thickness to act as an etch stop during a subsequent step to remove at least a portion of the hemispherical silicon grain layer, and is electrically conductive.

Abstract: A method for forming a volatile memory structure. A buried trench capacitor in each of a pair of neighboring trenches formed in a substrate. An asymmetric collar insulating layer is formed over an upper portion of the sidewall of each trench and has a high and a low level portions. A conductive layer is formed overlying the buried trench capacitor and below the surface of the substrate. The high level portion is adjacent to the substrate between the neighboring trenches and the low level portion is covered by the conductive layer. A dielectric layer is formed overlying the conductive layer. Two access transistors are formed on the substrate outside of the pair of the neighboring trenches, respectively, which have source/drain regions electrically connecting to the conductive layer. A volatile memory structure is also disclosed.

Abstract: A dynamic random access memory (DRAM) structure and a fabricating process thereof are provided. In the fabricating process, a channel region is formed with a doped region having identical conductivity as the substrate in a section adjacent to an isolation structure. The doped region is formed in a self-aligned process by conducting a tilt implantation implanting ions into the substrate through the upper portion of the capacitor trench adjacent to the channel region after forming the trench but before the definition of the active region.

Abstract: A method for manufacturing a trench capacitor that includes providing a semiconductor substrate, forming a deep trench in the substrate, forming a thin sacrificial layer on a surface of the trench, and forming a hemispherical silicon grain layer over the thin sacrificial layer, wherein the sacrificial layer has a thickness to act as an etch stop during a subsequent step to remove at least a portion of the hemispherical silicon grain layer, and is electrically conductive.

Abstract: A dynamic random access memory (DRAM) structure and a fabricating process thereof are provided. In the fabricating process, a channel region is formed with a doped region having identical conductivity as the substrate in a section adjacent to an isolation structure. The doped region is formed in a self-aligned process by conducting a tilt implantation implanting ions into the substrate through the upper portion of the capacitor trench adjacent to the channel region after forming the trench but before the definition of the active region.