Patents by Inventor Shih-Min Chang

Shih-Min Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12176387
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a capacitor over a substrate. The capacitor includes a plurality of conductive layers and a plurality of dielectric layers. The plurality of conductive layers and dielectric layers define a base structure and a first protrusion structure extending downward from the base structure towards a bottom surface of the substrate. The first protrusion structure comprises one or more surfaces defining a first cavity. A top of the first cavity is disposed below the base structure.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: December 24, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Li Cheng, Jyun-Ying Lin, Alexander Kalnitsky, Shih-Fen Huang, Shu-Hui Su, Ting-Chen Hsu, Tuo-Hsin Chien, Felix Ying-Kit Tsui, Shi-Min Wu, Yu-Chi Chang
  • Publication number: 20240395937
    Abstract: A source/drain region of a semiconductor device is formed using an epitaxial growth process. In an embodiment a first step comprises forming a bulk region of the source/drain region using a first precursor, a second precursor, and an etching precursor. A second step comprises cleaning the bulk region with the etchant along with introducing a shaping dopant to the bulk region in order to modify the crystalline structure of the exposed surfaces. A third step comprises forming a finishing region of the source/drain region using the first precursor, the second precursor, and the etching precursor.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Yi-Min Huang, Shih-Chieh Chang, Cheng-Han Lee
  • Patent number: 12142681
    Abstract: A source/drain region of a semiconductor device is formed using an epitaxial growth process. In an embodiment a first step comprises forming a bulk region of the source/drain region using a first precursor, a second precursor, and an etching precursor. A second step comprises cleaning the bulk region with the etchant along with introducing a shaping dopant to the bulk region in order to modify the crystalline structure of the exposed surfaces. A third step comprises forming a finishing region of the source/drain region using the first precursor, the second precursor, and the etching precursor.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: November 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Min Huang, Shih-Chieh Chang, Cheng-Han Lee
  • Publication number: 20240355597
    Abstract: An apparatus for ion beam etching is provided. An ion extractor separates a plasma source chamber from a process chamber. A gas inlet provides gas to the plasma source chamber. An RF power system provides RF power to the plasma source chamber. A process gas source and cleaning gas mixture source are connected to the gas inlet.
    Type: Application
    Filed: August 19, 2022
    Publication date: October 24, 2024
    Inventors: Chih-Yang CHANG, Raphael CASAES, Seokmin YUN, Shih-Yuan CHENG, Chih-Min LIN, Shuogang HUANG, Anurag Kumar MISHRA
  • Patent number: 12096657
    Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to associated semiconducting oxide transistors. The semiconducting oxide transistors may exhibit different device characteristics. Some of the semiconducting oxide transistors may be formed using a first oxide layer formed from a first semiconducting oxide material using first processing steps, whereas other semiconducting oxide transistors are formed using a second oxide layer formed from a second semiconducting oxide material using second processing steps different than the first processing steps. The display may include three or more different semiconducting oxide layers formed during different processing steps.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: September 17, 2024
    Assignee: Apple Inc.
    Inventors: Jung Yen Huang, Shinya Ono, Chin-Wei Lin, Akira Matsudaira, Cheng Min Hu, Chih Pang Chang, Ching-Sang Chuang, Gihoon Choo, Jiun-Jye Chang, Po-Chun Yeh, Shih Chang Chang, Yu-Wen Liu, Zino Lee
  • Patent number: 12062543
    Abstract: Methods of forming line-end extensions and devices having line-end extensions are provided. In some embodiments, a method includes forming a patterned photoresist on a first region of a hard mask layer. A line-end extension region is formed in the hard mask layer. The line-end extension region extends laterally outward from an end of the first region of the hard mask layer. The line-end extension region may be formed by changing a physical property of the hard mask layer at the line-end extension region.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: August 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Min Hsiao, Chien-Wen Lai, Ru-Gun Liu, Chih-Ming Lai, Shih-Ming Chang, Yung-Sung Yen, Yu-Chen Chang
  • Publication number: 20240241185
    Abstract: This disclosure provides an estimation method applied to a state of health of a battery, which executes a recharging to a battery when a battery voltage is lower than a threshold voltage. During the recharging, a battery state of health estimation procedure is performed from a first depth of discharge detection point to a second depth of discharge detection point. During the battery state of health estimation procedure, a voltage difference between a current battery voltage and an initial open-circuit voltage is accumulated over time from the first depth of discharge detection point to the second depth of discharge detection point to obtain an accumulation of current sampled voltage difference. An accumulation of estimated DC internal resistances can be equivalently obtained by the accumulation of current sampled voltage difference. Afterwards, the state of health of the battery can be determined based on the accumulation of estimated DC internal resistance.
    Type: Application
    Filed: July 11, 2023
    Publication date: July 18, 2024
    Inventors: Wen-Fan Chang, Chun-Chieh Li, Shih-Fa Hung, Jian-Min Chen
  • Patent number: 10676668
    Abstract: For a metal gate replacement integration scheme, the present disclosure describes removing a polysilicon gate electrode with a highly selective wet etch chemistry without damaging surrounding layers. For example, the wet etch chemistry can include one or more alkaline solvents with a steric hindrance amine structure, a buffer system that includes tetramethylammonium hydroxide (TMAH) and monoethanolamine (MEA), one or more polar solvents, and water.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Neng-Jye Yang, Kuo Bin Huang, Ming-Hsi Yeh, Shun Wu Lin, Yu-Wen Wang, Jian-Jou Lian, Shih Min Chang
  • Publication number: 20190119570
    Abstract: For a metal gate replacement integration scheme, the present disclosure describes removing a polysilicon gate electrode with a highly selective wet etch chemistry without damaging surrounding layers. For example, the wet etch chemistry can include one or more alkaline solvents with a steric hindrance amine structure, a buffer system that includes tetramethylammonium hydroxide (TMAH) and monoethanolamine (MEA), one or more polar solvents, and water.
    Type: Application
    Filed: December 14, 2018
    Publication date: April 25, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Neng-Jye YANG, Kuo Bin HUANG, Ming-Hsi YEH, Shun Wu LIN, Yu-Wen WANG, Jian-Jou LIAN, Shih Min CHANG
  • Patent number: 10179878
    Abstract: For a metal gate replacement integration scheme, the present disclosure describes removing a polysilicon gate electrode with a highly selective wet etch chemistry without damaging surrounding layers. For example, the wet etch chemistry can include one or more alkaline solvents with a steric hindrance amine structure, a buffer system that includes tetramethylammonium hydroxide (TMAH) and monoethanolamine (MEA), one or more polar solvents, and water.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: January 15, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Neng-Jye Yang, Kuo Bin Huang, Ming-Hsi Yeh, Shun Wu Lin, Yu-Wen Wang, Jian-Jou Lian, Shih Min Chang
  • Publication number: 20180171226
    Abstract: For a metal gate replacement integration scheme, the present disclosure describes removing a polysilicon gate electrode with a highly selective wet etch chemistry without damaging surrounding layers. For example, the wet etch chemistry can include one or more alkaline solvents with a steric hindrance amine structure, a buffer system that includes tetramethylammonium hydroxide (TMAH) and monoethanolamine (MEA), one or more polar solvents, and water.
    Type: Application
    Filed: July 24, 2017
    Publication date: June 21, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Neng-Jye YANG, Kuo Bin HUANG, Ming-Hsi YEH, Shun Wu LIN, Yu-Wen WANG, Jian-Jou LIAN, Shih Min CHANG
  • Publication number: 20150314322
    Abstract: A method of applying a protective coating to a substrate includes applying a surface treatment to edges of the substrate to increase surface wettability of the edges and/or preheating the substrate. A curable coating material is applied to the edges. Then, the substrate is spun to adjust a thickness and uniformity of the curable coating material applied on the substrate edges. The curable coating material is cured to form the protective coating on the substrate edges.
    Type: Application
    Filed: April 24, 2015
    Publication date: November 5, 2015
    Inventors: Shih-Min Chang, Cheng-Ta Chen, Chao-Yin Chuang, Hsien Li Lu
  • Publication number: 20150060401
    Abstract: A method of edge coating a batch of glass articles includes printing masks on surfaces of a glass sheet, where at least one of the masks is a patterned mask defining a network of separation paths. The glass sheet with the printed masks is divided into multiple glass articles along the separation paths. For at least a batch of the glass articles, the edges of the glass articles in the batch are finished to reduce roughness at the edges. Each finished edge is then etched with an etching medium to reduce and/or blunt flaws in the finished edge. A curable coating is simultaneously applied to the etched edges. The curable coatings are pre-cured. Then, the printed masks are removed from the glass articles with the curable coatings. After removing the printed masks, the pre-cured curable coatings are post-cured.
    Type: Application
    Filed: August 25, 2014
    Publication date: March 5, 2015
    Inventors: Shih-Min Chang, Cheng-Ta Chen, UeiJie Lin, Hsien Li Lu