Patents by Inventor Shih-Min Tseng

Shih-Min Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10957555
    Abstract: A process method for producing a photomask with double patterns. The processing method includes obtaining a contact distribution pattern, having multiple contacts. The contacts are sorted into multiple contact blocks in array type, pair type and isolation type. The contacts are decomposed into a first patterning group and a second patterning group, which are configured to interpose to each other. The numbers of contacts of the first patterning group and the second patterning group are equal within an error range. The first patterning group and the second patterning group are check whether or not having adjacent two contacts with a distance less than a minimum distance. If it is less than a minimum distance, one of the adjacent two contacts is changed from a current one of the first patterning group and the second patterning group to another. The first/second patterning groups are output to from first/second photomasks.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: March 23, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: Chien-Chin Huang, Shih-Min Tseng
  • Patent number: 10755022
    Abstract: An electronic apparatus and a layout method for an integrated circuit (IC) are provided. The layout method for the IC includes: receiving layout information, analyzing the layout information to obtain a plurality of blank areas in the IC; presetting a plurality of dummy blocks which respectively have a plurality of sizes; selecting at least one of the dummy blocks to fill in each of the blank areas based on a center position of each of the blank areas according to a size of each of the blank areas and generating updated layout information; performing a layout density checking operation on the updated layout information to generate a checking result; and shrinking sizes of a plurality of setting dummy blocks in the IC according to the checking result and generating output layout information.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: August 25, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Chien-Chin Huang, Shih-Min Tseng
  • Publication number: 20200152474
    Abstract: A process method for producing a photomask with double patterns. The processing method includes obtaining a contact distribution pattern, having multiple contacts. The contacts are sorted into multiple contact blocks in array type, pair type and isolation type. The contacts are decomposed into a first patterning group and a second patterning group, which are configured to interpose to each other. The numbers of contacts of the first patterning group and the second patterning group are equal within an error range. The first patterning group and the second patterning group are check whether or not having adjacent two contacts with a distance less than a minimum distance. If it is less than a minimum distance, one of the adjacent two contacts is changed from a current one of the first patterning group and the second patterning group to another. The first/second patterning groups are output to from first/second photomasks.
    Type: Application
    Filed: August 19, 2019
    Publication date: May 14, 2020
    Applicant: Winbond Electronics Corp.
    Inventors: Chien-Chin Huang, Shih-Min Tseng
  • Publication number: 20200125692
    Abstract: An electronic apparatus and a layout method for an integrated circuit (IC) are provided. The layout method for the IC includes: receiving layout information, analyzing the layout information to obtain a plurality of blank areas in the IC; presetting a plurality of dummy blocks which respectively have a plurality of sizes; selecting at least one of the dummy blocks to fill in each of the blank areas based on a center position of each of the blank areas according to a size of each of the blank areas and generating updated layout information; performing a layout density checking operation on the updated layout information to generate a checking result; and shrinking sizes of a plurality of setting dummy blocks in the IC according to the checking result and generating output layout information.
    Type: Application
    Filed: October 16, 2019
    Publication date: April 23, 2020
    Applicant: Winbond Electronics Corp.
    Inventors: Chien-Chin Huang, Shih-Min Tseng
  • Patent number: 9605345
    Abstract: A vertical furnace includes a heat treatment tube, at least one reactive gas inlet, first adiabatic plates and second adiabatic plates. The at least one reactive gas inlet is disposed at or near a bottom end of the heat treatment tube. The first adiabatic plates are stacked in the heat treatment tube, each of the first adiabatic plates having a flow channel structure for allowing a gas to pass through, in which all the corners in the flow channel structure are rounded. The second adiabatic plates are stacked below the first adiabatic plates in the heat treatment tube.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: March 28, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Eddy Lay, Shih-Min Tseng, Sheng-Wei Wu, Jen-Chung Chen, Shih-Fang Chen
  • Publication number: 20150053136
    Abstract: A vertical furnace includes a heat treatment tube, at least one reactive gas inlet, first adiabatic plates and second adiabatic plates. The at least one reactive gas inlet is disposed at or near a bottom end of the heat treatment tube. The first adiabatic plates are stacked in the heat treatment tube, each of the first adiabatic plates having a flow channel structure for allowing a gas to pass through, in which all the corners in the flow channel structure are rounded. The second adiabatic plates are stacked below the first adiabatic plates in the heat treatment tube.
    Type: Application
    Filed: August 23, 2013
    Publication date: February 26, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Eddy Lay, Shih-Min Tseng, Sheng-Wei Wu, Jen-Chung Chen, Shih-Fang Chen