Patents by Inventor Shih-Ming Liang

Shih-Ming Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240120388
    Abstract: Provided are structures and methods for forming structures with sloping surfaces of a desired profile. An exemplary method includes performing a first etch process to differentially etch a gate material to a recessed surface, wherein the recessed surface includes a first horn at a first edge, a second horn at a second edge, and a valley located between the first horn and the second horn; depositing an etch-retarding layer over the recessed surface, wherein the etch-retarding layer has a central region over the valley and has edge regions over the horns, and wherein the central region of the etch-retarding layer is thicker than the edge regions of the etch-retarding layer; and performing a second etch process to recess the horns to establish the gate material with a desired profile.
    Type: Application
    Filed: January 18, 2023
    Publication date: April 11, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Wei Yin, Tzu-Wen Pan, Yu-Hsien Lin, Jih-Sheng Yang, Shih-Chieh Chao, Chia Ming Liang, Yih-Ann Lin, Ryan Chia-Jen Chen
  • Patent number: 11929355
    Abstract: A mixed light light-emitting diode device includes first, second, and third chips, each having a first-type semiconductor layer with a first surface, a second-type semiconductor layer with a second surface opposite to the first surface, and a third surface indenting from the first surface and situated on the second-type semiconductor layer. The second and third chips have their first surfaces disposed above and facing the first surface of the first chip. A first-type electrode penetrates through the second and first surfaces of the first chip and contacts all first surfaces of first, second, and third chips. Two second-type electrodes each penetrates through the second and third surfaces of the first chip and connect the first chip to one of the second and third chips.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: March 12, 2024
    Assignee: MACROBLOCK, INC.
    Inventors: Shih-Sian Liang, Wei-Ming Tseng
  • Patent number: 8420488
    Abstract: A high voltage device is provided. The high voltage device includes a gate on a substrate, two source/drain regions in the substrate beside the gate, and a composite gate dielectric layer that includes at least two stacked continuous layers, extending from one side to another side of the gate. Wherein, the at least two stacked continuous layers is a combination of at least one thermal oxide layer and at least one chemical vapor deposited layer.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: April 16, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Yun-Han Ma, Ming-Tsung Lee, Shih-Ming Liang, Hwi-Huang Chen
  • Publication number: 20090065879
    Abstract: A high voltage device is provided. The high voltage device includes a gate on a substrate, two source/drain regions in the substrate beside the gate, and a composite gate dielectric layer that includes at least two stacked continuous layers, extending from one side to another side of the gate. Wherein, the at least two stacked continuous layers is a combination of at least one thermal oxide layer and at least one chemical vapor deposited layer.
    Type: Application
    Filed: September 11, 2007
    Publication date: March 12, 2009
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yun-Han Ma, Ming-Tsung Lee, Shih-Ming Liang, Hwi-Huang Chen