Abstract: The present invention provides a system and method for operating hybrid concurrent and switched dual-band low noise amplifiers. Embodiments use a concurrent design at the input block of a hybrid LNA to advantageously achieve better impedance matching while using a switch capacitor design at the output block to advantageously achieve a better gain than typical concurrent multiband LNAs. Embodiments might be integrated into wireless devices configured to simultaneously receive on multiple frequency bands while providing gains of 30 dB or more by combining the advantages of concurrent multiband LNAs with the advantages of switched multiband LNAs. In addition to the higher gains provided by embodiments of the hybrid LNA described herein, hybrid multiband LNAs according to embodiments of the present invention provide a smaller device footprint and power requirements than would be required for a receiver including multiple single-band LNAs for amplifying signals for each frequency band individually.

Abstract: A microfluidic control apparatus operating method is disclosed. The microfluidic control apparatus operating method is applied in a microfluidic control apparatus, and the microfluidic control apparatus includes a photoconductive material layer and a flow passage. The microfluidic control apparatus operating method includes steps of (a) when a light with a specific optical pattern is emitted toward the photoconductive material layer, at least three virtual electrodes being formed on the photoconductive material layer according to the specific optical pattern; (b) when the specific optical pattern changes, the at least three virtual electrodes also changing to generate an electro-osmotic force to control a moving state of a microfluid in the flow passage.

Abstract: A microfluidic control apparatus and operating method thereof. The microfluidic control apparatus includes a photoconductive material layer and a flow passage. When a light with a specific optical pattern is emitted toward the photoconductive material layer, at least three virtual electrodes are formed on the photoconductive material layer according to the specific optical pattern. The at least three virtual electrodes include a first virtual electrode, a second virtual electrode and a third virtual electrode disposed beside the first virtual electrode. There is a specific proportion among a distance between first virtual electrode and third virtual electrode, a width of first virtual electrode, a distance between first virtual electrode and second virtual electrode, and a width of second virtual electrode. When the specific optical pattern changes, the at least three virtual electrodes also change to generate an electro-osmotic force to control the moving state of a microfluid in a flow passage.

Abstract: Transceiver architectures for supporting multi-band radio frequencies are disclosed. According to one aspect of the present invention, a number of processing channels are designed, each for one specified carrier frequency. A number of switching means is provided to ensure that a processing channel is properly selected for a specified carrier frequency. Each of the processing channels includes at least an amplified and a low-pass filter, where the low-pass filter is automatically programmable in response to a wireless standard (e.g., Wi-Fi or WiMAX). A single voltage oscillator (VCO) is used to support operations of each of the processing channels.

Abstract: To provide greater flexibility in wireless communication design and implementation, a device and method for implementing media access control (MAC) layer functionality without using an embedded processor for MAC layer functions. A key table stores connection identification data and communicates the connection identification data to a transmit control module and a receive control module to configure and control data transmission and reception, respectively. This use of dedicated hardware, rather than an processor, to implement MAC functions simplifies the design and construction of devices which wirelessly communicate with each other.

Abstract: The present invention provides a system and method for operating hybrid concurrent and switched dual-band low noise amplifiers. Embodiments use a concurrent design at the input block of a hybrid LNA to advantageously achieve better impedance matching while using a switch capacitor design at the output block to advantageously achieve a better gain than typical concurrent multiband LNAs. Embodiments might be integrated into wireless devices configured to simultaneously receive on multiple frequency bands while providing gains of 30 dB or more by combining the advantages of concurrent multiband LNAs with the advantages of switched multiband LNAs. In addition to the higher gains provided by embodiments of the hybrid LNA described herein, hybrid multiband LNAs according to embodiments of the present invention provide a smaller device footprint and power requirements than would be required for a receiver including multiple single-band LNAs for amplifying signals for each frequency band individually.

Abstract: A decoder for decoding block error correction codes is described. The decoder includes a first search circuit to find roots of an error location polynomial corresponding to an error location and a second search circuit to find roots of an error location polynomial corresponding to an error location. A multiplexer is fed by the first search circuit and the second search circuit to produce an error location from the error location polynomial.

Abstract: A combined encoding/syndrome generating circuit is segmented into multiple-cell blocks that operate in parallel during encoding operations to produce interim sums. The interim sums are then combined to propagate a sum across the system, from the first cell to the last cell. Each cell includes a Galois Field multiplier and an associated update adder and register. A block of two cells includes two sets of associated Galois Field multipliers, registers and update adders, and a block feedback adder that produces the associated interim sum by adding together the products produced in parallel by each of the cells. A block with more than two cells includes additional feedback adders that operate in parallel to selectively combine the products produced by the plurality of cells, and produce an interim sum that includes a contribution from each of the cells in the block. The system then adds together the interim sums produced simultaneously by the various blocks, to propagate a sum across the system.

Abstract: In a hard disk drive, a two-level pipelined method of processing data errors which minimizes disk re-reads. In the first level, a sector is read and a syndrome is generated based on the ECC bits appended for that sector. If there are no errors, the next sector is read. However, if an error is detected, a flag is checked. If the flag is currently set, the disk drive is prevented from reading the next sector. If the flag is not set, the disk drive is allowed to proceed with reading the next sector; the syndrome is stored in a register; and hardware error correction is performed. If the error is corrected by the hardware circuit, the process repeats by reading the next sector. But if the hardware circuit cannot correct the error, a second level firmware error correction is eventually initiated for handling the error. The flag is set in order to prevent a subsequent syndrome from overwriting the syndrome currently in the register.

Abstract: An error correction system includes an encoder that uses a modified Reed-Solomon code to encode w-bit data symbols over GF(2.sup.w+i) and form a preliminary code with d-1 (w+i+1)-bit redundancy symbols. The preliminary code word is modified as necessary to set for each symbol a selected i bits to the same value as a corresponding i+1.sup.st bit. The preliminary code word also includes R pseudo redundancy symbols that are required for decoding the modified code word. The i+1 bits are then truncated from each of the code word symbols, to form a code word with w-bit symbols. The Galois Field GF(2.sup.w+i) is selected such that the elements of the field can be represented by (w+i+1)-bit symbols that are determined by a polynomial h(x) modulo an irreducible polynomial p(x), which isp(x)=x.sup.w+i +x.sup.w+i-1 + . . . +x.sup.1 +x.sup.0,with the polynomial h(x) representing a primitive element.

Abstract: The encoder/decoder system uses encoder hardware to encode data symbols and form a data code word. To decode, the system uses the same encoder hardware to determine a residue r(x), i.e. ##EQU1## where C.sub.r (x) is the retrieved code word and g(x) is the generator polynomial. If the residue is all zeros, the ECC code word is error-free and the system need not calculate the error syndrome. If the residue is non-zero, the encoder hardware is used, with various switches in different settings, to include certain multipliers in and exclude other multipliers from the further decoding operations of encoding the residue symbols to produce partial error syndromes that are the coefficients of the error syndrome polynomial.

Abstract: A two-level error correction encoder encodes m-bit data symbols in a first level of encoding in accordance with a distance d ECC over GF(2.sup.m+i) to produce (m+i)-bit ECC redundancy symbols and, during a second level of encoding, both modifies the set of ECC redundancy symbols, as necessary, to set i selected bits in each symbol in a predetermined truncation pattern and appends to the set of ECC symbols one or more pseudo redundancy symbols. The encoder includes d-1 Galois Field multipliers, and d-1 associated redundancy-symbol registers and an ECC symbol modifier lookup table that has stored therein information that the encoder uses during the second level of encoding. After the first level of encoding, the d-1 registers contain the (m+i)-bit ECC redundancy symbols.

Abstract: A method and apparatus for reconstructing syndromes in a disk drive system. In the present invention, two levels of handling data errors are provided. The first attempt at correcting errors is performed by a dedicated error correction hardware. The error correction is based on a syndrome which was generated as a function of the data and ECC bits. An ECC code is selected such that the resulting syndromes produces a repeating, cyclical pattern. If the hardware correction circuit is unable to correct the error, the original syndrome value is reconstructed by processing the syndrome a number of times to where its current value in the next cycle corresponds to the original value in a previous cycle. This reconstructed syndrome is then used by the processor to handle the persisting error under firmware control.