Patents by Inventor Shih-Ning TSAI

Shih-Ning TSAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12336443
    Abstract: A resistive random access memory is provided. The resistive random access memory includes a conductive line structure and a memory unit. The conductive line structure is disposed in an array area and a periphery circuit area. The memory unit is disposed on the conductive line structure in the array area. The memory unit includes a lower electrode, a resistive switching layer, and an upper electrode. The lower electrode is disposed on the conductive line structure. The resistive switching layer is disposed on the lower electrode. The upper electrode is disposed on the resistive switching layer. The upper surface of the conductive line structure is in direct contact with the lower electrode.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: June 17, 2025
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Chi-Ching Liu, Chih-Chao Huang, Shih-Ning Tsai
  • Patent number: 11793095
    Abstract: A resistive random access memory, including a first electrode layer and a second electrode layer disposed opposite to each other, a variable resistance layer located between the first electrode layer and the second electrode layer, an oxygen exchange layer located between the variable resistance layer and the second electrode layer, a vacancy-supplying layer surrounding a middle sidewall of the oxygen exchange layer; and a vacancy-driving electrode layer located on the vacancy-supply layer and surrounding an upper sidewall of the oxygen exchange layer, is provided. A method of fabricating the resistive random access memory is also provided.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: October 17, 2023
    Assignee: Winbond Electronics Corp.
    Inventors: Po-Yen Hsu, Bo-Lun Wu, Shih-Ning Tsai, Tse-Mian Kuo
  • Patent number: 11770985
    Abstract: Provided is a resistive random access memory (RRAM) including a first electrode layer and a second electrode layer disposed opposite to each other, a variable resistance layer located between the first electrode layer and the second electrode layer, an oxygen exchange layer located between the variable resistance layer and the second electrode layer, a conductive layer laterally surrounding a sidewall of the oxygen exchange layer, a first barrier layer located between the conductive layer and the oxygen exchange layer and between the oxygen exchange layer and the variable resistance layer, and a second barrier layer located between the conductive layer and the second electrode layer and between the second electrode layer and the oxygen exchange layer.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: September 26, 2023
    Assignee: Winbond Electronics Corp.
    Inventors: Po-Yen Hsu, Bo-Lun Wu, Shih-Ning Tsai
  • Publication number: 20230225228
    Abstract: A resistive random access memory is provided. The resistive random access memory includes a conductive line structure and a memory unit. The conductive line structure is disposed in an array area and a periphery circuit area. The memory unit is disposed on the conductive line structure in the array area. The memory unit includes a lower electrode, a resistive switching layer, and an upper electrode. The lower electrode is disposed on the conductive line structure. The resistive switching layer is disposed on the lower electrode. The upper electrode is disposed on the resistive switching layer. The upper surface of the conductive line structure is in direct contact with the lower electrode.
    Type: Application
    Filed: January 7, 2022
    Publication date: July 13, 2023
    Inventors: Chi-Ching LIU, Chih-Chao HUANG, Shih-Ning TSAI
  • Patent number: 11495637
    Abstract: Provided are a resistive random access memory and a method of manufacturing the same. The resistive random access memory includes a stacked structure and a bit line structure. The stacked structure is disposed on a substrate. The stacked structure includes a bottom electrode, a top electrode and a resistance-switching layer. The bottom electrode is disposed on the substrate. The top electrode is disposed on the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The bit line structure covers a top surface of the stacked structure and covers a portion of a sidewall of the stacked structure. The bit line structure is electrically connected to the stacked structure.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: November 8, 2022
    Assignee: Winbond Electronics Corp.
    Inventors: Po-Yen Hsu, Shih-Ning Tsai, Bo-Lun Wu, Tse-Mian Kuo
  • Publication number: 20220216401
    Abstract: A resistive random access memory, including a first electrode layer and a second electrode layer disposed opposite to each other, a variable resistance layer located between the first electrode layer and the second electrode layer, an oxygen exchange layer located between the variable resistance layer and the second electrode layer, a vacancy-supplying layer surrounding a middle sidewall of the oxygen exchange layer; and a vacancy-driving electrode layer located on the vacancy-supply layer and surrounding an upper sidewall of the oxygen exchange layer, is provided. A method of fabricating the resistive random access memory is also provided.
    Type: Application
    Filed: August 3, 2021
    Publication date: July 7, 2022
    Applicant: Winbond Electronics Corp.
    Inventors: Po-Yen Hsu, Bo-Lun Wu, Shih-Ning Tsai, Tse-Mian Kuo
  • Publication number: 20220093858
    Abstract: Provided is a resistive random access memory (RRAM) including a first electrode layer and a second electrode layer disposed opposite to each other, a variable resistance layer located between the first electrode layer and the second electrode layer, an oxygen exchange layer located between the variable resistance layer and the second electrode layer, a conductive layer laterally surrounding a sidewall of the oxygen exchange layer, a first barrier layer located between the conductive layer and the oxygen exchange layer and between the oxygen exchange layer and the variable resistance layer, and a second barrier layer located between the conductive layer and the second electrode layer and between the second electrode layer and the oxygen exchange layer.
    Type: Application
    Filed: September 21, 2020
    Publication date: March 24, 2022
    Applicant: Winbond Electronics Corp.
    Inventors: Po-Yen Hsu, Bo-Lun Wu, Shih-Ning Tsai
  • Publication number: 20220005868
    Abstract: Provided are a resistive random access memory and a method of manufacturing the same. The resistive random access memory includes a stacked structure and a bit line structure. The stacked structure is disposed on a substrate. The stacked structure includes a bottom electrode, a top electrode and a resistance-switching layer. The bottom electrode is disposed on the substrate. The top electrode is disposed on the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The bit line structure covers a top surface of the stacked structure and covers a portion of a sidewall of the stacked structure. The bit line structure is electrically connected to the stacked structure.
    Type: Application
    Filed: July 1, 2020
    Publication date: January 6, 2022
    Applicant: Winbond Electronics Corp.
    Inventors: Po-Yen Hsu, Shih-Ning Tsai, Bo-Lun Wu, Tse-Mian Kuo
  • Patent number: 11177321
    Abstract: A resistive random access memory is provided. The resistive random access memory includes a substrate, a first electrode formed on the substrate, a second electrode formed on the substrate and located on one side of the first electrode, a first metal oxide layer formed on sidewalls of the second electrode, a first control layer formed between the first electrode and the first metal oxide layer, and a second control layer formed on the first control layer and located between the first electrode and the first metal oxide layer.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: November 16, 2021
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Po-Yen Hsu, Bo-Lun Wu, Shih-Ning Tsai, Cheng-Hui Tu
  • Patent number: 11011702
    Abstract: A memory device includes a first electrode, a resistive switching layer, a cap layer, a protective layer, and a second electrode. The resistive switching layer is disposed over the first electrode. The cap layer is disposed over the resistive switching layer, wherein the bottom surface of the cap layer is smaller than the top surface of the resistive switching layer. The protective layer is disposed over the resistive switching layer and surrounds the cap layer. At least a portion of the second electrode is disposed over the cap layer and covers the protective layer.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: May 18, 2021
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Bo-Lun Wu, Shih-Ning Tsai, Po-Yen Hsu
  • Publication number: 20210126053
    Abstract: A resistive random access memory is provided. The resistive random access memory includes a substrate, a first electrode formed on the substrate, a second electrode formed on the substrate and located on one side of the first electrode, a first metal oxide layer formed on sidewalls of the second electrode, a first control layer formed between the first electrode and the first metal oxide layer, and a second control layer formed on the first control layer and located between the first electrode and the first metal oxide layer.
    Type: Application
    Filed: October 23, 2019
    Publication date: April 29, 2021
    Inventors: Po-Yen HSU, Bo-Lun WU, Shih-Ning TSAI, Cheng-Hui TU
  • Publication number: 20210043836
    Abstract: A memory device includes a first electrode, a resistive switching layer, a cap layer, a protective layer, and a second electrode. The resistive switching layer is disposed over the first electrode. The cap layer is disposed over the resistive switching layer, wherein the bottom surface of the cap layer is smaller than the top surface of the resistive switching layer. The protective layer is disposed over the resistive switching layer and surrounds the cap layer. At least a portion of the second electrode is disposed over the cap layer and covers the protective layer.
    Type: Application
    Filed: August 7, 2019
    Publication date: February 11, 2021
    Inventors: Bo-Lun WU, Shih-Ning TSAI, Po-Yen HSU