Patents by Inventor Shih-Ping Chiao

Shih-Ping Chiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11227925
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a transistor. The transistor includes a first source/drain (S/D) region, a second S/D region and a gate structure. The first S/D region is defined in a first well on a double diffusion layer, wherein the first well and the double diffusion layer define a diode at a junction therebetween, wherein an anode of the diode and the first S/D region form an open circuit therebetween. The gate structure is between the first S/D region and the second S/D region.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: January 18, 2022
    Assignee: PTEK TECHNOLOGY CO., LTD.
    Inventors: Ming Tang, Shih Ping Chiao
  • Patent number: 10636902
    Abstract: The present disclosure provides a power MOSFET device including a multiple gated transistor disposed over a substrate. The multiple gated transistor includes a first transistor cell having a first drain pillar, a first source pillar, and a first gate conductor disposed between the first drain pillar and the first source pillar. The multiple gated transistor further includes a second transistor cell having a second drain pillar, a second source pillar, and a second gate conductor disposed between the second drain pillar and the second source pillar. The multiple gated transistor further includes a first insulator disposed over the substrate and between the first gate conductor and the second gate conductor. The first insulator electrically insulates the second gate conductor from the first gate conductor.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: April 28, 2020
    Assignee: PTEK Technology Co., Ltd.
    Inventors: Ming Tang, Shih Ping Chiao
  • Publication number: 20200091337
    Abstract: The present disclosure provides a power MOSFET device including a multiple gated transistor disposed over a substrate. The multiple gated transistor includes a first transistor cell having a first drain pillar, a first source pillar, and a first gate conductor disposed between the first drain pillar and the first source pillar. The multiple gated transistor further includes a second transistor cell having a second drain pillar, a second source pillar, and a second gate conductor disposed between the second drain pillar and the second source pillar. The multiple gated transistor further includes a first insulator disposed over the substrate and between the first gate conductor and the second gate conductor. The first insulator electrically insulates the second gate conductor from the first gate conductor.
    Type: Application
    Filed: September 13, 2018
    Publication date: March 19, 2020
    Inventors: Ming TANG, Shih Ping CHIAO
  • Publication number: 20180301554
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a transistor. The transistor includes a first source/drain (S/D) region, a second S/D region and a gate structure. The first S/D region is defined in a first well on a double diffusion layer, wherein the first well and the double diffusion layer define a diode at a junction therebetween, wherein an anode of the diode and the first S/D region form an open circuit therebetween. The gate structure is between the first S/D region and the second S/D region.
    Type: Application
    Filed: December 29, 2017
    Publication date: October 18, 2018
    Inventors: Ming TANG, Shih Ping CHIAO
  • Patent number: 8816445
    Abstract: A power MOSFET device includes at least one MOSFET unit disposed over a substrate, wherein the MOSFET unit includes a plurality of cells and a boundary surrounding the cells. In one embodiment of the present invention, the cell is configured to provide a unit current, and comprises at least one source pillar and at least one drain pillar, a gate conductor surrounding the source pillar and the drain pillar, and an insulating structure electrically separating the gate conductor from the source pillar and the drain pillar, wherein the gate conductor extends from the cell to the boundary.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: August 26, 2014
    Assignee: Ptek Technology Co., Ltd.
    Inventors: Ming Tang, Shih Ping Chiao
  • Publication number: 20140197475
    Abstract: A power MOSFET device includes at least one MOSFET unit disposed over a substrate, wherein the MOSFET unit includes a plurality of cells and a boundary surrounding the cells. In one embodiment of the present invention, the cell is configured to provide a unit current, and comprises at least one source pillar and at least one drain pillar, a gate conductor surrounding the source pillar and the drain pillar, and an insulating structure electrically separating the gate conductor from the source pillar and the drain pillar, wherein the gate conductor extends from the cell to the boundary.
    Type: Application
    Filed: January 14, 2013
    Publication date: July 17, 2014
    Applicant: PTEK TECHNOLOGY CO., LTD.
    Inventors: MING TANG, SHIH PING CHIAO
  • Patent number: 8299526
    Abstract: An integrated circuit includes a power MOS transistor which comprises a drain region, a trench gate, a source region, a well region, a deep well region and a substrate region. The drain region has a doping region of a first conductivity type connected to a drain electrode. The trench gate has an insulating layer and extends into the drain region. The source region has a doping region of the first conductivity type connected to a source electrode. The well region is doped with a second conductivity type, formed under the source region, and connected to the source electrode. The deep well region is doped with the first conductivity type and is formed under the drain region and the well region. The substrate region is doped with the second conductivity type and is formed under the deep well region. The drain region is formed at one side of the trench gate and the source region is formed at the opposing side of the trench gate such that the trench gate laterally connects the source region and the drain region.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: October 30, 2012
    Assignee: PTEK Technology Co., Ltd.
    Inventors: Ming Tang, Shih-Ping Chiao
  • Patent number: 8211766
    Abstract: A trench-typed power MOS transistor comprises a trench-typed gate area, which includes a gate conductor and an isolation layer. A thin sidewall region of the isolation layer is formed between the gate conductor and a well region. A thick sidewall region of the isolation layer is formed between the gate conductor and a double diffusion region. A thick bottom region of the isolation layer is formed between the gate conductor and a deep well region.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: July 3, 2012
    Assignee: PTEK Technology Co., Ltd.
    Inventors: Ming Tang, Shih-Ping Chiao
  • Publication number: 20120100683
    Abstract: A trench-typed power MOS transistor comprises a trench-typed gate area, which includes a gate conductor and an isolation layer. A thin sidewall region of the isolation layer is formed between the gate conductor and a well region. A thick sidewall region of the isolation layer is formed between the gate conductor and a double diffusion region. A thick bottom region of the isolation layer is formed between the gate conductor and a deep well region.
    Type: Application
    Filed: December 29, 2011
    Publication date: April 26, 2012
    Applicant: PTEK TECHNOLOGY CO., LTD.
    Inventors: MING TANG, SHIH-PING CHIAO
  • Patent number: 8159025
    Abstract: A trench-typed power MOS transistor comprises a trench-typed gate area, which includes a gate conductor and an isolation layer. A thin sidewall region of the isolation layer is formed between the gate conductor and a well region. A thick sidewall region of the isolation layer is formed between the gate conductor and a double diffusion region. A thick bottom region of the isolation layer is formed between the gate conductor and a deep well region.
    Type: Grant
    Filed: January 6, 2010
    Date of Patent: April 17, 2012
    Assignee: PTEK Technology Co., Ltd.
    Inventors: Ming Tang, Shih-Ping Chiao
  • Patent number: 8134205
    Abstract: The present invention discloses a layout structure of a transistor unit of a power MOS transistor, wherein the layout structure comprises a drain area, a plurality of body areas, a plurality of source areas and a gate area. The plurality of body areas surround the drain area. The plurality of source areas extend from the perimeters of the plurality of body areas in an anisotropic manner. The gate area is disposed between the drain area and the plurality of source areas. The contacts of the drain area, the plurality of body areas and the plurality of source areas are all disposed on the same side of the layout structure.
    Type: Grant
    Filed: January 6, 2010
    Date of Patent: March 13, 2012
    Assignee: PTEK Technology Co., Ltd.
    Inventors: Ming Tang, Shih-Ping Chiao
  • Publication number: 20110163378
    Abstract: The present invention discloses a layout structure of a transistor unit of a power MOS transistor, wherein the layout structure comprises a drain area, a plurality of body areas, a plurality of source areas and a gate area. The plurality of body areas surround the drain area. The plurality of source areas extend from the perimeters of the plurality of body areas in an anisotropic manner. The gate area is disposed between the drain area and the plurality of source areas. The contacts of the drain area, the plurality of body areas and the plurality of source areas are all disposed on the same side of the layout structure.
    Type: Application
    Filed: January 6, 2010
    Publication date: July 7, 2011
    Applicant: PTEK TECHNOLOGY CO., LTD.
    Inventors: MING TANG, SHIH PING CHIAO
  • Publication number: 20110163374
    Abstract: A trench-typed power MOS transistor comprises a trench-typed gate area, which includes a gate conductor and an isolation layer. A thin sidewall region of the isolation layer is formed between the gate conductor and a well region. A thick sidewall region of the isolation layer is formed between the gate conductor and a double diffusion region. A thick bottom region of the isolation layer is formed between the gate conductor and a deep well region.
    Type: Application
    Filed: January 6, 2010
    Publication date: July 7, 2011
    Applicant: PTEK TECHNOLOGY CO., LTD.
    Inventors: MING TANG, SHIH-PING CHIAO
  • Publication number: 20100276751
    Abstract: An integrated circuit includes a power MOS transistor which comprises a drain region, a trench gate, a source region, a well region, a deep well region and a substrate region. The drain region has a doping region of a first conductivity type connected to a drain electrode. The trench gate has an insulating layer and extends into the drain region. The source region has a doping region of the first conductivity type connected to a source electrode. The well region is doped with a second conductivity type, formed under the source region, and connected to the source electrode. The deep well region is doped with the first conductivity type and is formed under the drain region and the well region. The substrate region is doped with the second conductivity type and is formed under the deep well region. The drain region is formed at one side of the trench gate and the source region is formed at the opposing side of the trench gate such that the trench gate laterally connects the source region and the drain region.
    Type: Application
    Filed: July 16, 2010
    Publication date: November 4, 2010
    Applicant: PTEK TECHNOLOGY CO., LTD.
    Inventors: MING TANG, SHIH-PING CHIAO
  • Patent number: 7781832
    Abstract: A power MOS transistor comprises a drain region, a trench gate, a source region, a well region, a deep well region and a substrate region. The drain region has a doping region of a first conductivity type connected to a drain electrode. The trench gate has an insulating layer and extends into the drain region. The source region has a doping region of the first conductivity type connected to a source electrode. The well region is doped with a second conductivity type, formed under the source region, and connected to the source electrode. The deep well region is doped with the first conductivity type and is formed under the drain region and the well region. The substrate region is doped with the second conductivity type and is formed under the deep well region. The drain region is formed at one side of the trench gate and the source region is formed at the opposing side of the trench gate such that the trench gate laterally connects the source region and the drain region.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: August 24, 2010
    Assignee: PTEK Technology Co., Ltd.
    Inventors: Ming Tang, Shih-Ping Chiao
  • Publication number: 20090294846
    Abstract: A power MOS transistor comprises a drain region, a trench gate, a source region, a well region, a deep well region and a substrate region. The drain region has a doping region of a first conductivity type connected to a drain electrode. The trench gate has an insulating layer and extends into the drain region. The source region has a doping region of the first conductivity type connected to a source electrode. The well region is doped with a second conductivity type, formed under the source region, and connected to the source electrode. The deep well region is doped with the first conductivity type and is formed under the drain region and the well region. The substrate region is doped with the second conductivity type and is formed under the deep well region. The drain region is formed at one side of the trench gate and the source region is formed at the opposing side of the trench gate such that the trench gate laterally connects the source region and the drain region.
    Type: Application
    Filed: May 28, 2008
    Publication date: December 3, 2009
    Applicant: PTEK TECHNOLOGY CO., LTD.
    Inventors: MING TANG, SHIH-PING CHIAO