Patents by Inventor Shih-Ping Chiao
Shih-Ping Chiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11227925Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a transistor. The transistor includes a first source/drain (S/D) region, a second S/D region and a gate structure. The first S/D region is defined in a first well on a double diffusion layer, wherein the first well and the double diffusion layer define a diode at a junction therebetween, wherein an anode of the diode and the first S/D region form an open circuit therebetween. The gate structure is between the first S/D region and the second S/D region.Type: GrantFiled: December 29, 2017Date of Patent: January 18, 2022Assignee: PTEK TECHNOLOGY CO., LTD.Inventors: Ming Tang, Shih Ping Chiao
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Patent number: 10636902Abstract: The present disclosure provides a power MOSFET device including a multiple gated transistor disposed over a substrate. The multiple gated transistor includes a first transistor cell having a first drain pillar, a first source pillar, and a first gate conductor disposed between the first drain pillar and the first source pillar. The multiple gated transistor further includes a second transistor cell having a second drain pillar, a second source pillar, and a second gate conductor disposed between the second drain pillar and the second source pillar. The multiple gated transistor further includes a first insulator disposed over the substrate and between the first gate conductor and the second gate conductor. The first insulator electrically insulates the second gate conductor from the first gate conductor.Type: GrantFiled: September 13, 2018Date of Patent: April 28, 2020Assignee: PTEK Technology Co., Ltd.Inventors: Ming Tang, Shih Ping Chiao
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Publication number: 20200091337Abstract: The present disclosure provides a power MOSFET device including a multiple gated transistor disposed over a substrate. The multiple gated transistor includes a first transistor cell having a first drain pillar, a first source pillar, and a first gate conductor disposed between the first drain pillar and the first source pillar. The multiple gated transistor further includes a second transistor cell having a second drain pillar, a second source pillar, and a second gate conductor disposed between the second drain pillar and the second source pillar. The multiple gated transistor further includes a first insulator disposed over the substrate and between the first gate conductor and the second gate conductor. The first insulator electrically insulates the second gate conductor from the first gate conductor.Type: ApplicationFiled: September 13, 2018Publication date: March 19, 2020Inventors: Ming TANG, Shih Ping CHIAO
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Publication number: 20180301554Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a transistor. The transistor includes a first source/drain (S/D) region, a second S/D region and a gate structure. The first S/D region is defined in a first well on a double diffusion layer, wherein the first well and the double diffusion layer define a diode at a junction therebetween, wherein an anode of the diode and the first S/D region form an open circuit therebetween. The gate structure is between the first S/D region and the second S/D region.Type: ApplicationFiled: December 29, 2017Publication date: October 18, 2018Inventors: Ming TANG, Shih Ping CHIAO
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Patent number: 8816445Abstract: A power MOSFET device includes at least one MOSFET unit disposed over a substrate, wherein the MOSFET unit includes a plurality of cells and a boundary surrounding the cells. In one embodiment of the present invention, the cell is configured to provide a unit current, and comprises at least one source pillar and at least one drain pillar, a gate conductor surrounding the source pillar and the drain pillar, and an insulating structure electrically separating the gate conductor from the source pillar and the drain pillar, wherein the gate conductor extends from the cell to the boundary.Type: GrantFiled: January 14, 2013Date of Patent: August 26, 2014Assignee: Ptek Technology Co., Ltd.Inventors: Ming Tang, Shih Ping Chiao
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Publication number: 20140197475Abstract: A power MOSFET device includes at least one MOSFET unit disposed over a substrate, wherein the MOSFET unit includes a plurality of cells and a boundary surrounding the cells. In one embodiment of the present invention, the cell is configured to provide a unit current, and comprises at least one source pillar and at least one drain pillar, a gate conductor surrounding the source pillar and the drain pillar, and an insulating structure electrically separating the gate conductor from the source pillar and the drain pillar, wherein the gate conductor extends from the cell to the boundary.Type: ApplicationFiled: January 14, 2013Publication date: July 17, 2014Applicant: PTEK TECHNOLOGY CO., LTD.Inventors: MING TANG, SHIH PING CHIAO
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Patent number: 8299526Abstract: An integrated circuit includes a power MOS transistor which comprises a drain region, a trench gate, a source region, a well region, a deep well region and a substrate region. The drain region has a doping region of a first conductivity type connected to a drain electrode. The trench gate has an insulating layer and extends into the drain region. The source region has a doping region of the first conductivity type connected to a source electrode. The well region is doped with a second conductivity type, formed under the source region, and connected to the source electrode. The deep well region is doped with the first conductivity type and is formed under the drain region and the well region. The substrate region is doped with the second conductivity type and is formed under the deep well region. The drain region is formed at one side of the trench gate and the source region is formed at the opposing side of the trench gate such that the trench gate laterally connects the source region and the drain region.Type: GrantFiled: July 16, 2010Date of Patent: October 30, 2012Assignee: PTEK Technology Co., Ltd.Inventors: Ming Tang, Shih-Ping Chiao
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Patent number: 8211766Abstract: A trench-typed power MOS transistor comprises a trench-typed gate area, which includes a gate conductor and an isolation layer. A thin sidewall region of the isolation layer is formed between the gate conductor and a well region. A thick sidewall region of the isolation layer is formed between the gate conductor and a double diffusion region. A thick bottom region of the isolation layer is formed between the gate conductor and a deep well region.Type: GrantFiled: December 29, 2011Date of Patent: July 3, 2012Assignee: PTEK Technology Co., Ltd.Inventors: Ming Tang, Shih-Ping Chiao
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Publication number: 20120100683Abstract: A trench-typed power MOS transistor comprises a trench-typed gate area, which includes a gate conductor and an isolation layer. A thin sidewall region of the isolation layer is formed between the gate conductor and a well region. A thick sidewall region of the isolation layer is formed between the gate conductor and a double diffusion region. A thick bottom region of the isolation layer is formed between the gate conductor and a deep well region.Type: ApplicationFiled: December 29, 2011Publication date: April 26, 2012Applicant: PTEK TECHNOLOGY CO., LTD.Inventors: MING TANG, SHIH-PING CHIAO
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Patent number: 8159025Abstract: A trench-typed power MOS transistor comprises a trench-typed gate area, which includes a gate conductor and an isolation layer. A thin sidewall region of the isolation layer is formed between the gate conductor and a well region. A thick sidewall region of the isolation layer is formed between the gate conductor and a double diffusion region. A thick bottom region of the isolation layer is formed between the gate conductor and a deep well region.Type: GrantFiled: January 6, 2010Date of Patent: April 17, 2012Assignee: PTEK Technology Co., Ltd.Inventors: Ming Tang, Shih-Ping Chiao
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Patent number: 8134205Abstract: The present invention discloses a layout structure of a transistor unit of a power MOS transistor, wherein the layout structure comprises a drain area, a plurality of body areas, a plurality of source areas and a gate area. The plurality of body areas surround the drain area. The plurality of source areas extend from the perimeters of the plurality of body areas in an anisotropic manner. The gate area is disposed between the drain area and the plurality of source areas. The contacts of the drain area, the plurality of body areas and the plurality of source areas are all disposed on the same side of the layout structure.Type: GrantFiled: January 6, 2010Date of Patent: March 13, 2012Assignee: PTEK Technology Co., Ltd.Inventors: Ming Tang, Shih-Ping Chiao
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Publication number: 20110163378Abstract: The present invention discloses a layout structure of a transistor unit of a power MOS transistor, wherein the layout structure comprises a drain area, a plurality of body areas, a plurality of source areas and a gate area. The plurality of body areas surround the drain area. The plurality of source areas extend from the perimeters of the plurality of body areas in an anisotropic manner. The gate area is disposed between the drain area and the plurality of source areas. The contacts of the drain area, the plurality of body areas and the plurality of source areas are all disposed on the same side of the layout structure.Type: ApplicationFiled: January 6, 2010Publication date: July 7, 2011Applicant: PTEK TECHNOLOGY CO., LTD.Inventors: MING TANG, SHIH PING CHIAO
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Publication number: 20110163374Abstract: A trench-typed power MOS transistor comprises a trench-typed gate area, which includes a gate conductor and an isolation layer. A thin sidewall region of the isolation layer is formed between the gate conductor and a well region. A thick sidewall region of the isolation layer is formed between the gate conductor and a double diffusion region. A thick bottom region of the isolation layer is formed between the gate conductor and a deep well region.Type: ApplicationFiled: January 6, 2010Publication date: July 7, 2011Applicant: PTEK TECHNOLOGY CO., LTD.Inventors: MING TANG, SHIH-PING CHIAO
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Publication number: 20100276751Abstract: An integrated circuit includes a power MOS transistor which comprises a drain region, a trench gate, a source region, a well region, a deep well region and a substrate region. The drain region has a doping region of a first conductivity type connected to a drain electrode. The trench gate has an insulating layer and extends into the drain region. The source region has a doping region of the first conductivity type connected to a source electrode. The well region is doped with a second conductivity type, formed under the source region, and connected to the source electrode. The deep well region is doped with the first conductivity type and is formed under the drain region and the well region. The substrate region is doped with the second conductivity type and is formed under the deep well region. The drain region is formed at one side of the trench gate and the source region is formed at the opposing side of the trench gate such that the trench gate laterally connects the source region and the drain region.Type: ApplicationFiled: July 16, 2010Publication date: November 4, 2010Applicant: PTEK TECHNOLOGY CO., LTD.Inventors: MING TANG, SHIH-PING CHIAO
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Patent number: 7781832Abstract: A power MOS transistor comprises a drain region, a trench gate, a source region, a well region, a deep well region and a substrate region. The drain region has a doping region of a first conductivity type connected to a drain electrode. The trench gate has an insulating layer and extends into the drain region. The source region has a doping region of the first conductivity type connected to a source electrode. The well region is doped with a second conductivity type, formed under the source region, and connected to the source electrode. The deep well region is doped with the first conductivity type and is formed under the drain region and the well region. The substrate region is doped with the second conductivity type and is formed under the deep well region. The drain region is formed at one side of the trench gate and the source region is formed at the opposing side of the trench gate such that the trench gate laterally connects the source region and the drain region.Type: GrantFiled: May 28, 2008Date of Patent: August 24, 2010Assignee: PTEK Technology Co., Ltd.Inventors: Ming Tang, Shih-Ping Chiao
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Publication number: 20090294846Abstract: A power MOS transistor comprises a drain region, a trench gate, a source region, a well region, a deep well region and a substrate region. The drain region has a doping region of a first conductivity type connected to a drain electrode. The trench gate has an insulating layer and extends into the drain region. The source region has a doping region of the first conductivity type connected to a source electrode. The well region is doped with a second conductivity type, formed under the source region, and connected to the source electrode. The deep well region is doped with the first conductivity type and is formed under the drain region and the well region. The substrate region is doped with the second conductivity type and is formed under the deep well region. The drain region is formed at one side of the trench gate and the source region is formed at the opposing side of the trench gate such that the trench gate laterally connects the source region and the drain region.Type: ApplicationFiled: May 28, 2008Publication date: December 3, 2009Applicant: PTEK TECHNOLOGY CO., LTD.Inventors: MING TANG, SHIH-PING CHIAO