Patents by Inventor Shih-Ping Lin

Shih-Ping Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250064345
    Abstract: A gait evaluating system including a processor is provided. The processor identifies whether a gait type of the user belongs to a normal gait, a non-neuropathic gait or a neuropathic gait based on step feature values of a user and walking limb feature values of the user. In response to that the gait type of the user belongs to the non-neuropathic gait, the processor controls the display panel to display a first auxiliary information, a second auxiliary information, and a third auxiliary information. The first auxiliary information indicates a potential sarcopenia of the user. The second auxiliary information indicates a dietary guideline for muscle building and muscle strengthening. The third auxiliary information shows a motion instruction video for regaining or maintaining muscle strength of the user.
    Type: Application
    Filed: October 18, 2024
    Publication date: February 27, 2025
    Applicant: Industrial Technology Research Institute
    Inventors: Je-Ping Hu, Keng-Hsun Lin, Shih-Fang Yang Mao, Pin-Chou Li, Jian-Hong Wu, Szu-Ju Li, Hui-Yu Cho, Yu-Chang Chen, Yen-Nien Lu, Jyun-Siang Hsu, Nien-Ya Lee, Kuan-Ting Ho, Ming-Chieh Tsai, Ching-Yu Huang
  • Patent number: 12230545
    Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.
    Type: Grant
    Filed: November 30, 2023
    Date of Patent: February 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuei-Yu Kao, Chen-Yui Yang, Hsien-Chung Huang, Chao-Cheng Chen, Shih-Yao Lin, Chih-Chung Chiu, Chih-Han Lin, Chen-Ping Chen, Ke-Chia Tseng, Ming-Ching Chang
  • Publication number: 20250052088
    Abstract: A vertical cable rail panel includes first and second rails, and each comprises a channel and a plurality of spaced apart through holes. An internal member is disposed within one of the channels and defines a bearing surface and a first opening. A rigid support member vertically extends between the first rail and the second rail. A vertical cable includes a cable member, a first swage fitting, and a second swage fitting. The first end of the vertical cable extends through one of the plurality of through holes in the first rail and extends through the first opening in the internal member. A swage fitting is secured to each end of the vertical cable. A threaded member is associated with one of the swage fittings and the internal member, and adjusting the threaded member adjusts a tension in the vertical cable.
    Type: Application
    Filed: October 21, 2024
    Publication date: February 13, 2025
    Applicant: Fortress Iron, LP
    Inventors: Kevin T. Burt, Matthew Carlyle Sherstad, Shih-Te Lin, Hua-Ping Huang
  • Publication number: 20250041340
    Abstract: The present invention provides a method of treating targeted abnormal cells that are resistant, refractory, insensitive, non-responsive, or inadequately responsive to an ingredient, as well as cytotoxic cells used therein, comprising administering an effective amount of the ingredient-complexed cytotoxic cells to a subject with the disease.
    Type: Application
    Filed: December 12, 2022
    Publication date: February 6, 2025
    Applicant: Acepodia Biotechnologies Ltd.
    Inventors: CHING-WEN HSIAO, ZIH-FEI CHENG, TAI-SHENG WU, YAN-LIANG LIN, HAO-KANG LI, SAI-WEN TANG, HSIU-PING YANG, SHIH-CHIA HSIAO
  • Publication number: 20250040214
    Abstract: A semiconductor fabrication method includes: forming an epitaxial stack including at least one sacrificial epitaxial layer and at least one channel epitaxial layer; forming a plurality of fins in the epitaxial stack; performing tuning operations to prevent a width of the sacrificial epitaxial layer expanding beyond a width of the channel epitaxial layer during operations to form isolation features; forming the isolation features between the plurality of fins, wherein the width of the sacrificial epitaxial layer does not expand beyond the width of the channel epitaxial layer; forming a sacrificial gate stack; forming gate sidewall spacers on sidewalls of the sacrificial gate stack; forming inner spacers around the sacrificial epitaxial layer and the channel epitaxial layer; forming source/drain features; removing the sacrificial gate stack and sacrificial epitaxial layer; and forming a replacement metal gate, wherein the metal gate is shielded from the source/drain features.
    Type: Application
    Filed: July 27, 2023
    Publication date: January 30, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Yu Kao, Shih-Yao Lin, Chiung-Yu Cho, Po-Yuan Tseng, Min-Chiao Lin, Chen-Ping Chen, Chih-Han Lin, Ming-Ching Chang
  • Patent number: 12204163
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: February 5, 2024
    Date of Patent: January 21, 2025
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Publication number: 20250022914
    Abstract: A method of forming a nanosheet FET is provided. A plurality of first and second semiconductor layers are alternately formed on a substrate. The first and second semiconductor layers are patterned into a plurality of stacks of semiconductor layers separate from each other by a space along a direction. Each stack of semiconductor layers has a cross-sectional view along the direction gradually widening towards the substrate. An epitaxial feature is formed in each of the spaces. The patterned second semiconductor layers are then removed from each of the stacks of semiconductor layers.
    Type: Application
    Filed: July 14, 2023
    Publication date: January 16, 2025
    Inventors: Kuei-Yu KAO, Shih-Yao LIN, Chiung-Yu CHO, Chen-Ping CHEN, Chih-Han LIN, Ming-Ching CHANG
  • Publication number: 20240203918
    Abstract: A chip stack structure is provided. The chip stack structure includes a first chip including a first substrate and a first interconnect structure over the first substrate. The chip stack structure includes a second chip over and bonded to the first chip. The second chip has a second interconnect structure and a second substrate over the second interconnect structure. The chip stack structure includes an insulating layer over the second interconnect structure and surrounding the second substrate. The chip stack structure includes a conductive plug penetrating through the insulating layer to the second interconnect structure.
    Type: Application
    Filed: January 6, 2023
    Publication date: June 20, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chuei-Tang WANG, Tso-Jung CHANG, Shih-Ping LIN, Jeng-Shien HSIEH, Chih-Peng LIN, Chieh-Yen CHEN, Chen-Hua YU
  • Publication number: 20240206193
    Abstract: A package structure and a formation method are provided. The method includes bonding a first memory-containing chip structure to a second memory-containing chip structure through dielectric-to-dielectric bonding and metal-to-metal bonding. The method also includes bonding a logic control chip structure to the second memory-containing chip structure through dielectric-to-dielectric bonding and metal-to-metal bonding. The logic control chip structure is formed using a more advanced technology node than the second memory-containing chip structure.
    Type: Application
    Filed: January 9, 2023
    Publication date: June 20, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang WANG, Tso-Jung CHANG, Wen-Shiang LIAO, Jeng-Shien HSIEH, Chih-Peng LIN, Shih-Ping LIN, Chieh-Yen CHEN, Chen-Hua YU
  • Publication number: 20240079392
    Abstract: A semiconductor structure includes a first tier, a redistribution circuit structure, and a second tier. The first tier includes at least one first die. The redistribution circuit structure is disposed on the first tier and electrically coupled to the at least one first die, where the redistribution circuit structure has a multi-layer structure and includes a vertical connection structure continuously extending from a first side of the redistribution circuit structure to a second side of the redistribution circuit structure, and the first side is opposite to the second side along a stacking direction of the first tier and the redistribution circuit structure. The second tier includes a plurality of second dies, and is disposed on and electrically coupled to the redistribution circuit structure.
    Type: Application
    Filed: January 10, 2023
    Publication date: March 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang WANG, Tso-Jung Chang, Jeng-Shien Hsieh, Shih-Ping Lin, Chih-Peng Lin, Chieh-Yen Chen, Chen-Hua Yu
  • Publication number: 20240047365
    Abstract: A package structure and a formation method are provided. The method includes disposing a first chip structure and a second chip structure over a carrier substrate. The method also includes forming an interconnection structure directly over and contacting the first chip structure and the second chip structure. The interconnection structure has multiple dielectric layers and multiple conductive features. One of the conductive features extends across a first edge of the first chip structure and a second edge of the second chip structure and is electrically connecting the first chip structure and the second chip structure. The method further includes directly bonding a third chip structure to the interconnection structure through dielectric-to-dielectric bonding and metal-to-metal bonding.
    Type: Application
    Filed: January 5, 2023
    Publication date: February 8, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang WANG, Tso-Jung CHANG, Jeng-Shien HSIEH, Shih-Ping LIN, Chieh-Yen CHEN, Chen-Hua YU
  • Patent number: 11801146
    Abstract: An artificial intervertebral disc is configured to be inserted between adjacent human vertebrae. The artificial intervertebral disc includes a first connection block, a joint block and a second connection block. The joint block has a convex surface and a rear surface. The rear surface of the joint block is stacked on the first connection block. The second connection block is slidably stacked on the convex surface of the joint block, such that the second connection block is movable relative to the first connection block. In addition, the convex surface is a curved surface, and the convex surface is arranged off-axis with respect to the rear surface.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: October 31, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Fang-Chieh Chang, Pei-I Tsai, Shih-Ping Lin, Ming-Jun Li, Chih-Chieh Huang, Hsin-Hsin Shen, Meng-Huang Wu
  • Publication number: 20230172720
    Abstract: An artificial intervertebral disc is configured to be inserted between adjacent human vertebrae. The artificial intervertebral disc includes a first connection block, a joint block and a second connection block. The joint block has a convex surface and a rear surface. The rear surface of the joint block is stacked on the first connection block. The second connection block is slidably stacked on the convex surface of the joint block, such that the second connection block is movable relative to the first connection block. In addition, the convex surface is a curved surface, and the convex surface is arranged off-axis with respect to the rear surface.
    Type: Application
    Filed: December 14, 2021
    Publication date: June 8, 2023
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Fang-Chieh CHANG, Pei-I TSAI, Shih-Ping LIN, Ming-Jun LI, Chih-Chieh HUANG, Hsin-Hsin SHEN, Meng-Huang WU
  • Patent number: 11619845
    Abstract: This disclosure relates to a display device which includes a light transmissible layer and a second material. The light transmissible layer includes a first material, wherein the first material generates a first color transformation from a first color to a second color after being exposed under a light of the first wavelength range. The second material is either included in the light transmissible layer or has a projective area overlapped with the light transmissible layer. The second material generates a second color transformation from the second color to the first color after being exposed under a light of the first wavelength range.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: April 4, 2023
    Assignee: AU OPTRONICS CORPORATION
    Inventor: Shih-Ping Lin
  • Patent number: 11596450
    Abstract: A low-profile offset-type spinal fusion device includes a first screw, a connection base, a nut and a compression part. The first screw has an external thread and a flange. The connection base includes a penetration part and a connection part disposed no higher than the penetration part, and can sleeve the first screw through a first hole of the penetration part to contact the flange with opposite ends of the first screw protruding out of the first hole. The nut, used to engage the first screw, has a bottom surface to contact against the penetration part. When the first screw is installed by penetrating the first hole, the nut and the flange are located to opposite ends of the first hole. The compression part is to screw into a cavity of the connection part for depressing a connecting bar tightly in the cavity.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: March 7, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Hsin-Hsin Shen, Pei-I Tsai, Chih-Chieh Huang, Kuo-Yi Yang, Yi-Hung Wen, Wei-Lun Fan, Fang-Jie Jang, Shih-Ping Lin
  • Publication number: 20220175423
    Abstract: A low-profile offset-type spinal fusion device includes a first screw, a connection base, a nut and a compression part. The first screw has an external thread and a flange. The connection base includes a penetration part and a connection part disposed no higher than the penetration part, and can sleeve the first screw through a first hole of the penetration part to contact the flange with opposite ends of the first screw protruding out of the first hole. The nut, used to engage the first screw, has a bottom surface to contact against the penetration part. When the first screw is installed by penetrating the first hole, the nut and the flange are located to opposite ends of the first hole. The compression part is to screw into a cavity of the connection part for depressing a connecting bar tightly in the cavity.
    Type: Application
    Filed: August 31, 2021
    Publication date: June 9, 2022
    Inventors: HSIN-HSIN SHEN, PEI-I TSAI, CHIH-CHIEH HUANG, KUO-YI YANG, YI-HUNG WEN, WEI-LUN FAN, FANG-JIE JANG, SHIH-PING LIN
  • Publication number: 20220175432
    Abstract: A bone screw includes an external screw thread, an internal supporter structure and a porous layer. The internal supporter structure is inside the external screw thread. The internal supporter structure includes a screw thread supporter or a polygonal wall supporter. The porous layer is on a surface of the internal supporter structure. Therefore, the bone screw has an increased strength and also provides postoperative healing effect.
    Type: Application
    Filed: December 4, 2020
    Publication date: June 9, 2022
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Hsin-Hsin SHEN, Pei-I TSAI, Kuo-Yi YANG, Fang-Jie JANG, An-Li CHEN, Shih-Ping LIN, Chih-Chieh HUANG, Yi-Hung WEN, Wei-Lun FAN, Shin-I HUANG
  • Publication number: 20220079639
    Abstract: One embodiment of the disclosure relates to a flexible bone fixation device including two first fixation parts and a first flexible spanning part, connected between the two first fixation parts. The first flexible spanning part has a plurality of first cuts spaced apart by one another.
    Type: Application
    Filed: December 4, 2020
    Publication date: March 17, 2022
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Fang-Jie JANG, Pei-I TSAI, An-Li CHEN, Wei-Lun FAN, Shih-Ping LIN, Yi-Hung WEN, De-Yau LIN, Shun-Mao YANG, Ying-Hao SU, Huan-Jang KO
  • Patent number: 11141262
    Abstract: A bone implant includes at least one spiral and at least one pillar. The spiral surrounds an accommodating space. The pillar is disposed in the accommodating space and connected to the spiral. The pillar has at least one notch.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: October 12, 2021
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Pei-I Tsai, Hsin-Hsin Shen, Kuo-Yi Yang, Chih-Chieh Huang, Shih-Ping Lin, De-Yau Lin
  • Publication number: 20210088847
    Abstract: This disclosure relates to a display device which includes a light transmissible layer and a second material. The light transmissible layer includes a first material, wherein the first material generates a first color transformation from a first color to a second color after being exposed under a light of the first wavelength range. The second material is either included in the light transmissible layer or has a projective area overlapped with the light transmissible layer. The second material generates a second color transformation from the second color to the first color after being exposed under a light of the first wavelength range.
    Type: Application
    Filed: July 17, 2020
    Publication date: March 25, 2021
    Inventor: Shih-Ping LIN