Patents by Inventor Shih Shigjong KUO

Shih Shigjong KUO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Instruction for determining histograms
    Patent number: 10908908
    Abstract: A processor is described having a functional unit of an instruction execution pipeline. The functional unit has comparison bank circuitry and adder circuitry. The comparison bank circuitry is to compare one or more elements of a first input vector against an element of a second input vector. The adder circuitry is coupled to the comparison bank circuitry to add the number of elements of the second input vector that match a value of the first input vector on an element by element basis of the first input vector.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventor: Shih Shigjong Kuo
  • Instruction for determining histograms
    Patent number: 10908907
    Abstract: A processor is described having a functional unit of an instruction execution pipeline. The functional unit has comparison bank circuitry and adder circuitry. The comparison bank circuitry is to compare one or more elements of a first input vector against an element of a second input vector. The adder circuitry is coupled to the comparison bank circuitry to add the number of elements of the second input vector that match a value of the first input vector on an element by element basis of the first input vector.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventor: Shih Shigjong Kuo
  • Instruction for determining histograms
    Patent number: 10416998
    Abstract: A processor is described having a functional unit of an instruction execution pipeline. The functional unit has comparison bank circuitry and adder circuitry. The comparison bank circuitry is to compare one or more elements of a first input vector against an element of a second input vector. The adder circuitry is coupled to the comparison bank circuitry to add the number of elements of the second input vector that match a value of the first input vector on an element by element basis of the first input vector.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: September 17, 2019
    Assignee: Intel Corporation
    Inventor: Shih Shigjong Kuo
  • INSTRUCTION FOR DETERMINING HISTOGRAMS
    Publication number: 20190095210
    Abstract: A processor is described having a functional unit of an instruction execution pipeline. The functional unit has comparison bank circuitry and adder circuitry. The comparison bank circuitry is to compare one or more elements of a first input vector against an element of a second input vector. The adder circuitry is coupled to the comparison bank circuitry to add the number of elements of the second input vector that match a value of the first input vector on an element by element basis of the first input vector.
    Type: Application
    Filed: October 29, 2018
    Publication date: March 28, 2019
    Inventor: Shih Shigjong KUO
  • INSTRUCTION FOR DETERMINING HISTOGRAMS
    Publication number: 20190065185
    Abstract: A processor is described having a functional unit of an instruction execution pipeline. The functional unit has comparison bank circuitry and adder circuitry. The comparison bank circuitry is to compare one or more elements of a first input vector against an element of a second input vector. The adder circuitry is coupled to the comparison bank circuitry to add the number of elements of the second input vector that match a value of the first input vector on an element by element basis of the first input vector.
    Type: Application
    Filed: October 29, 2018
    Publication date: February 28, 2019
    Inventor: Shih Shigjong KUO
  • Instruction for Determining Histograms
    Publication number: 20180067741
    Abstract: A processor is described having a functional unit of an instruction execution pipeline. The functional unit has comparison bank circuitry and adder circuitry. The comparison bank circuitry is to compare one or more elements of a first input vector against an element of a second input vector. The adder circuitry is coupled to the comparison bank circuitry to add the number of elements of the second input vector that match a value of the first input vector on an element by element basis of the first input vector.
    Type: Application
    Filed: October 30, 2017
    Publication date: March 8, 2018
    Inventor: Shih Shigjong KUO
  • Instruction for determining histograms
    Patent number: 9804839
    Abstract: A processor is described having a functional unit of an instruction execution pipeline. The functional unit has comparison bank circuitry and adder circuitry. The comparison bank circuitry is to compare one or more elements of a first input vector against an element of a second input vector. The adder circuitry is coupled to the comparison bank circuitry to add the number of elements of the second input vector that match a value of the first input vector on an element by element basis of the first input vector.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: October 31, 2017
    Assignee: Intel Corporation
    Inventor: Shih Shigjong Kuo
  • Instruction for Determining Histograms
    Publication number: 20140189320
    Abstract: A processor is described having a functional unit of an instruction execution pipeline. The functional unit has comparison bank circuitry and adder circuitry. The comparison bank circuitry is to compare one or more elements of a first input vector against an element of a second input vector. The adder circuitry is coupled to the comparison bank circuitry to add the number of elements of the second input vector that match a value of the first input vector on an element by element basis of the first input vector.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Inventor: Shih Shigjong KUO