Abstract: A decoder and an operation method thereof are provided. The decoder includes a pre-unit, a database, a data filter, and a scheduler. The pre-unit provides packet information of a data stream. The database records a plurality of parameter sets. The scheduler fetches the corresponding parameter sets from the database according to the packet information, and saves the parameter sets into the data filter. The data filter compares the data stream with the saved parameter sets and outputs a comparing result. Therefore, the present invention reduces the cost of the decoder.

Abstract: A receiver having a first clock signal is provided. The first frequency of the first clock signal is adjusted to be close to a second frequency of a second clock signal of a transmitter. The receiver includes a clock generator, a processor and a controller. The clock generator is for generating the first clock signal. The processor is for outputting a first control signal to control the clock generator to adjust the first frequency to be close to the second frequency when an absolute value of a current difference between the first and the second frequencies at a current time point is larger than a threshold. The controller is for outputting a second control signal to control the clock generator when the absolute value of the current difference is smaller than the threshold, so as to reduce the load of the processor.

Abstract: A descrambling apparatus and a descrambling method to descramble a scrambled data in a receiver of a digital TV system are provided. The descrambling apparatus comprises: a receiving module, a storing module, a comparator, a retrieving module and a descrambler. The receiving module receives a packet, wherein the packet comprises a key-status field, a packet identifier field and a scrambled data; the storing module stores a key data and a formerly received packet data; the comparator compares the formerly received packet data and a key-status value of the key-status field to generate a compare result; the retrieving module retrieves a descramble key from the key data and the formerly received packet data according to the compare result, the key-status value and a packet identifier value of the packet identifier field; and the descrambler descrambles the scrambled data according to the descramble key to generate a descrambled data.

Abstract: A device for controlling program stream flow is described. The device is capable of saving power during computation. The device may include a de-multiplex unit and a direct memory access controller. The de-multiplex unit, for de-multiplexing a plurality of data, may include a request module for generating a request signal. The direct memory access controller is for receiving the request signal. The direct memory access controller obtains a plurality of data from a bus and sends the plurality of data to the de-multiplex unit according to the request signal.

Abstract: A de-multiplexer is disclosed. A transport stream de-multiplexer includes a plurality of input buffers (211-21N) each receiving bytes from a plurality of packets in a corresponding transport stream, a main buffer (230) for temporal storage of said packets and an input arbiter temporally allotting a space of at least one packet in the main buffer to one of said packets when receiving a request to store a first byte of said packets into said main buffer.

Abstract: An apparatus and a method for an efficient audio/video (AV) synchronization are provided. The apparatus includes a parser, a frame memory, a video start code (VSC) detector and a video decoder. The parser is used for analyzing a packetized elementary stream (PES) and outputting a video stream, an address information and at least one time stamp, in which the video stream includes a frame and at least one VSC corresponding to the frame. The frame memory is used for temporarily storing the video stream according to the address information. The VSC detector is used for retrieving the VSC of the video stream. The video decoder is used for selecting the frame from the frame memory according to the VSC and the address information provided by the VSC detector.

Abstract: A flexible length decoder including a plurality of data filter units and a control unit is provided. The data filter units perform a comparing operation on a data stream according its corresponding pattern and output a comparing result. The control unit controls the configurations of the data filter units. If the space of any one of the data filter units for storing the pattern is not enough to record the required pattern, the control unit combines two or more data filter units into an equivalent data filter unit, such that the equivalent data filter unit stores the pattern and performs the comparing operation.

Abstract: A decoder and an operation method thereof are provided. The decoder includes a pre-unit, a database, a data filter, and a scheduler. The pre-unit provides packet information of a data stream. The database records a plurality of parameter sets. The scheduler fetches the corresponding parameter sets from the database according to the packet information, and saves the parameter sets into the data filter. The data filter compares the data stream with the saved parameter sets and outputs a comparing result. Therefore, the present invention reduces the cost of the decoder.

Abstract: A receiver having a first clock signal is provided. The first frequency of the first clock signal is adjusted to be close to a second frequency of a second clock signal of a transmitter. The receiver includes a clock generator, a processor and a controller. The clock generator is for generating the first clock signal. The processor is for outputting a first control signal to control the clock generator to adjust the first frequency to be close to the second frequency when an absolute value of a current difference between the first and the second frequencies at a current time point is larger than a threshold. The controller is for outputting a second control signal to control the clock generator when the absolute value of the current difference is smaller than the threshold, so as to reduce the load of the processor.