Abstract: A recipe management system associates a selected process recipe with a recipe group and checks to see if other recipes of the recipe group have been updated since the selected recipe was last run. If another recipe of the recipe group has been run and adjustments have been made to the other recipe based on an analysis of a manufacturing or test run, the recipe management system identifies the selected recipe as requiring an update. The recipe management system sends error reports noting the discrepancy between a parameter setting changed in the test run and needing adjustment in the selected run. The recipe management system also effectuates the needed adjustments to the selected recipe before the selected recipe is allowed to be used in the manufacturing environment.

Abstract: A statistical process control method for monitoring and controlling semiconductor manufacturing processing operations is provided. For a chosen processing operation, multiple measurement sites are used to generate data of a measurable characteristic that is impacted by and associated with the processing operation. The data from the sites is compared over time and one or more outlier sites are identified. The outlier sites are the sites at which the data values are most divergent from the rest of the data. Algorithms are used to mathematically compare the outlier sites to the other sites to produce a comparative index. The comparative index is monitored graphically or otherwise to identify changes in the processing operation, and corrective actions are taken.

Abstract: A statistical process control method for monitoring and controlling semiconductor manufacturing processing operations is provided. For a chosen processing operation, multiple measurement sites are used to generate data of a measurable characteristic that is impacted by and associated with the processing operation. The data from the sites is compared over time and one or more outlier sites are identified. The outlier sites are the sites at which the data values are most divergent from the rest of the data. Algorithms are used to mathematically compare the outlier sites to the other sites to produce a comparative index. The comparative index is monitored graphically or otherwise to identify changes in the processing operation, and corrective actions are taken.

Abstract: A statistical process control method for monitoring and controlling semiconductor manufacturing processing operations is provided. For a chosen processing operation, multiple measurement sites are used to generate data of a measurable characteristic that is impacted by and associated with the processing operation. The data from the sites is compared over time and one or more outlier sites are identified. The outlier sites are the sites at which the data values are most divergent from the rest of the data. Algorithms are used to mathematically compare the outlier sites to the other sites to produce a comparative index. The comparative index is monitored graphically or otherwise to identify changes in the processing operation, and corrective actions are taken.

Abstract: A recipe management system associates a selected process recipe with a recipe group and checks to see if other recipes of the recipe group have been updated since the selected recipe was last run. If another recipe of the recipe group has been run and adjustments have been made to the other recipe based on an analysis of a manufacturing or test run, the recipe management system identifies the selected recipe as requiring an update. The recipe management system sends error reports noting the discrepancy between a parameter setting changed in the test run and needing adjustment in the selected run. The recipe management system also effectuates the needed adjustments to the selected recipe before the selected recipe is allowed to be used in the manufacturing environment.

Abstract: An integrated circuit having post passivation interconnections with a second connection pattern is disclosed. A passivation layer (preferably made of a non-oxide material) is formed over the integrated circuit already having a first plurality of contact pads in a first connection pattern. A buffer layer is then formed over the passivation layer. The buffer layer preferably is a silicon oxide layer with a thickness substantially smaller than a thickness of the passivation layer. A post passivation metal layer is deposited over the buffer layer. A second plurality of contact pads as part of the second connection pattern is formed in the post passivation metal layer.

Abstract: A novel test device and method for calibrating the alignment of a laser beam emitted from a laser metrology tool with respect to a target area on a substrate. The test device includes a laser-sensitive material having a calibration pattern that includes a target point. When the tool is properly adjusted, the laser beam strikes the target point and is released to production. If the laser beam misses the target point, the tool is re-adjusted and re-tested until the laser beam strikes the target point.

Abstract: A method of forming a metal-filled opening in a semiconductor or other submicron device substrate includes forming a conductive bulk layer over the substrate surface and in the opening, wherein the conductive bulk layer has a first grain size. A conductive cap layer is formed over the conductive bulk layer, the conductive cap layer having a second grain size that is substantially smaller than the first grain size. At least one of the conductive bulk and cap layers are then planarized to form a planar surface that is substantially coincident with the substrate surface.

Abstract: An electropolishing method for removing potential device-contaminating particles from a wafer, is disclosed. The method includes immersing the wafer in an electropolishing electrolyte solution and removing defects and particles from the wafer by rotational friction between the wafer and the electrolyte solution in combination with electrolysis. The method is effective in removing particles from via openings of all sizes, including via openings having a width smaller than about 0.2 ?m.

Abstract: An integrated circuit having post passivation interconnections with a second connection pattern is disclosed. A passivation layer (preferably made of a non-oxide material) is formed over the integrated circuit already having a first plurality of contact pads in a first connection pattern. A buffer layer is then formed over the passivation layer. The buffer layer preferably is a silicon oxide layer with a thickness substantially smaller than a thickness of the passivation layer. A post passivation metal layer is deposited over the buffer layer. A second plurality of contact pads as part of the second connection pattern is formed in the post passivation metal layer.

Abstract: A method for forming a copper dual damascene with improved copper migration resistance and improved electrical resistivity including providing a semiconductor wafer including upper and lower dielectric insulating layers separated by a middle etch stop layer; forming a dual damascene opening extending through a thickness of the upper and lower dielectric insulating layers wherein an upper trench line portion extends through the upper dielectric insulating layer thickness and partially through the middle etch stop layer; blanket depositing a barrier layer including at least one of a refractory metal and refractory metal nitride to line the dual damascene opening; carrying out a remote plasma etch treatment of the dual damascene opening to remove a bottom portion of the barrier layer to reveal an underlying conductive area; and, filling the dual damascene opening with copper to provide a substantially planar surface.

Abstract: A method of forming post passivation interconnects for an integrated circuit is disclosed. A passivation layer of a non-oxide material is formed over the integrated circuit. A buffer layer is then formed over the passivation layer. The buffer layer preferably is a silicon oxide layer with a thickness substantially smaller than a thickness of the passivation layer. A post passivation metal layer is deposited over the buffer layer and a connection pattern is formed in the post passivation metal layer.

Abstract: A novel test device and method for calibrating the alignment of a laser beam emitted from a laser metrology tool with respect to a target area on a substrate. The test device includes a laser-sensitive material having a calibration pattern that includes a target point. When the tool is properly adjusted, the laser beam strikes the target point and is released to production. If the laser beam misses the target point, the tool is re-adjusted and re-tested until the laser beam strikes the target point.

Abstract: A method of forming a metal-filled opening in a semiconductor or other submicron device substrate includes forming a conductive bulk layer over the substrate surface and in the opening, wherein the conductive bulk layer has a first grain size. A conductive cap layer is formed over the conductive bulk layer, the conductive cap layer having a second grain size that is substantially smaller than the first grain size. At least one of the conductive bulk and cap layers are then planarized to form a planar surface that is substantially coincident with the substrate surface.

Abstract: A method for forming a copper dual damascene with improved copper migration resistance and improved electrical resistivity including providing a semiconductor wafer including upper and lower dielectric insulating layers separated by a middle etch stop layer; forming a dual damascene opening extending through a thickness of the upper and lower dielectric insulating layers wherein an upper trench line portion extends through the upper dielectric insulating layer thickness and partially through the middle etch stop layer; blanket depositing a barrier layer including at least one of a refractory metal and refractory metal nitride to line the dual damascene opening; carrying out a remote plasma etch treatment of the dual damascene opening to remove a bottom portion of the barrier layer to reveal an underlying conductive area; and, filling the dual damascene opening with copper to provide a substantially planar surface.

Abstract: An electropolishing method for removing potential device-contaminating particles from a wafer, is disclosed. The method includes immersing the wafer in an electropolishing electrolyte solution and removing defects and particles from the wafer by rotational friction between the wafer and the electrolyte solution in combination with electrolysis. The method is effective in removing particles from via openings of all sizes, including via openings having a width smaller than about 0.2 ?m.

Abstract: A method of forming post passivation interconnects for an integrated circuit is disclosed. A passivation layer of a non-oxide material is formed over the integrated circuit. A buffer layer is then formed over the passivation layer. The buffer layer preferably is a silicon oxide layer with a thickness substantially smaller than a thickness of the passivation layer. A post passivation metal layer is deposited over the buffer layer and a connection pattern is formed in the post passivation metal layer.

Abstract: For 0.18 micron technology, it is common practice to use silicon oxynitride as an anti-reflective layer for defining the via etch patterns. It has however been found that, using current technology, residual particles of oxynitride get left behind. The present invention solves this problem by subjecting the surface from which the silicon oxynitride was removed to a high pressure rinse of an aqueous solution that includes a surfactant such as tetramethyl ammonium hydroxide or isopropyl alcohol. These surfactants serve to modify the hydrophobic behavior of the silicon oxynitride particles so that they no longer cling to the surface.

Abstract: A method and system is disclosed for reducing slurry usage in a chemical mechanical polishing operation utilizing at least one polishing pad thereof. Slurry can be intermittently supplied to a chemical mechanical polishing device. The slurry is generally flushed so that a portion of said slurry is trapped in a plurality of pores of at least one polishing pad associated with said chemical mechanical polishing device, wherein only a minimum amount of said slurry necessary is utilized to perform said chemical mechanical polishing operation, thereby reducing slurry usage and maintaining a consistent level of slurry removal rate performance and a decrease in particle defects thereof. The present invention thus discloses a method and system for intermittently delivering slurry to a chemical mechanical polishing device in a manner that significantly conserves slurry usage.

Abstract: A method for improving thickness uniformity on a semiconductor wafer during a chemical mechanical polishing process capable of eliminating a wafer edge collapsing defect is described. In the method, slurry solution is removed from a peripheral edge portion of less than 10 mm wide on the surface of the polishing pad such that a concentration of the slurry can be effectively reduced in the peripheral region. The reduced slurry solution leads to a reduction in the removal rate on the wafer surface. The removal of slurry from the peripheral region can further be achieved by a mechanical means. A suitable width of the peripheral region of the polishing pad to be sprayed by an edge sprayer is less than 10 mm, and preferably between about 3 mm and about 5 mm. A suitable solvent to be sprayed is deionized water.