Abstract: A system may include a gimbal defining a plurality of pockets, where each pocket may include a first portion and a second portion that extends between the first portion and a base of the pocket. The second portion may have a greater diameter than the first portion. The system may include a plurality of conditioning disks, where each conditioning disk is seated within the first portion of a respective pocket. The system may include a plurality of gaskets, where each gasket is seated within the second portion of a respective pocket. The system may include a plurality o-rings, each o-ring disposed between a peripheral edge of one of the plurality of conditioning disks and a lateral wall of one of the plurality of pockets. The system may include a plurality of shoulder screws for coupling the gimbal with one of the plurality of gaskets and a conditioning disk.

Abstract: A multiple detection system is applied to a vehicle and includes a contact-type detection module adapted to generate a contact-type detection datum, a contactless-type detection module adapted to generate a contactless-type detection datum, and an operation processor electrically connected with the contact-type detection module and the contactless-type detection module in a wire manner or in a wireless manner. The operation processor sets at least one of the contact-type detection datum and the contactless-type detection datum according to an environmental status of the vehicle to be a main detection result of the multiple detection system, and further sets the other detection datum to be an auxiliary detection result of the multiple detection system, for acquiring a passenger feature inside the vehicle.

Abstract: A backlight module includes a light source, a first prism sheet disposed on the light source, and a light type adjustment sheet disposed on a side of the first prism sheet away from the light source and including a base and multiple light type adjustment structures. The multiple light type adjustment structures are disposed on the first surface of the base. Each light type adjustment structure has a first structure surface and a second structure surface connected to each other. The first structure surface of each light type adjustment structure and the first surface of the base form a first base angle therebetween, and the second structure surface of each light type adjustment structure and the first surface of the base form a second base angle therebetween. The angle of the first base angle is different from the angle of the second base angle.

Abstract: An apparatus and a method for neural network computation are provided. The apparatus for neural network computation includes a first neuron circuit and a second neuron circuit. The first neuron circuit is configured to execute a neural network computation of at least one computing layer with a fixed feature pattern in a neural network algorithm. The second neuron circuit is configured to execute the neural network computation of at least one computing layer with an unfixed feature pattern in the neural network algorithm. The performance of the first neuron circuit is greater than that of the second neuron circuit.

Abstract: A digital compute-in-memory (DCIM) macro includes a memory cell array and an arithmetic logic unit (ALU). The memory cell array stores weight data of a neural network. The ALU receives parallel bits of a same input channel in an activation input, and generates a convolution computation output of the parallel bits and target weight data in the memory cell array.

Abstract: A display may include an array of pixels such as light-emitting diode pixels. The pixels may include multiple circuitry decks that each include one or more circuit components such as transistors, capacitors, and/or resistors. The circuitry decks may be vertically stacked. Each circuitry deck may include a planarization layer formed from a siloxane material that conforms to underlying components and provides a planar upper surface. In this way, circuitry components may be vertically stacked to mitigate the size of each pixel footprint. The circuitry components may include capacitors that include both a high-k dielectric layer and a low-k dielectric layer. The display pixel may include a via with a width of less than 1 micron.

Abstract: A digital compute-in-memory (DCIM) system includes a first DCIM macro. The first DCIM macro includes a first memory cell array and a first arithmetic logic unit (ALU). The first memory cell array has N rows that are configured to store weight data of a neural network in a single weight data download session, wherein N is a positive integer not smaller than two. The first ALU is configured to receive a first activation input, and perform convolution operations upon the first activation input and a single row of weight data selected from the N rows of the first memory cell array to generate first convolution outputs.

Abstract: A method for forming a semiconductor device structure includes forming nanostructures over a substrate. The method also includes forming a gate structure wrapped around the nanostructures. The method also includes forming source/drain epitaxial structures over opposite sides of the nanostructures. The method also includes forming a first interlayer dielectric structure over the source/drain epitaxial structures. The method also includes removing the first interlayer dielectric structure. The method also includes forming a recess in the source/drain epitaxial structures. The method also includes forming a silicide structure in the recess. The method also includes forming a second interlayer dielectric structure over the silicide structure.

Abstract: Disclosed herein is a method for treating and/or preventing a lymphangiogenesis-associated disease in a subject, including administering to the subject a therapeutically effective amount of a dihydrolipoic acid (DHLA)-coated gold nanocluster about 0.1 to 10 nm in diameter. Also disclosed is a method for promoting lymphangiogenesis in a subject, including administering to the subject an effective amount of said DHLA-coated gold nanocluster.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a photodiode region disposed within a substrate having a first semiconductor material. A second semiconductor material is disposed on the substrate. A doped region is between the substrate and a part of the second semiconductor material. The second semiconductor material includes a projection extending outward from a surface of the second semiconductor material and towards the photodiode region. The projection extends through the doped region.

Abstract: SRAM designs based on GAA transistors are disclosed that provide flexibility for increasing channel widths of transistors at scaled IC technology nodes and relax limits on SRAM performance optimization imposed by FinFET-based SRAMs. GAA-based SRAM cells described have active region layouts with active regions shared by pull-down GAA transistors and pass-gate GAA transistors. A width of shared active regions that correspond with the pull-down GAA transistors are enlarged with respect to widths of the shared active regions that correspond with the pass-gate GAA transistors. A ratio of the widths is tuned to obtain ratios of pull-down transistor effective channel width to pass-gate effective channel width greater than 1, increase an on-current of pull-down GAA transistors relative to an on-current of pass-gate GAA transistors, decrease a threshold voltage of pull-down GAA transistors relative to a threshold voltage of pass-gate GAA transistors, and/or increases a ? ratio of an SRAM cell.

Abstract: An optical member driving mechanism for connecting an optical member is provided, including a fixed portion and a first adhesive member. The fixed portion includes a first member and a second member, wherein the first member is fixedly connected to the second member via the first adhesive member.

Abstract: A display may have an array of pixels. Display driver circuitry may supply data and control signals to the pixels. Each pixel may have seven transistors, a capacitor, and a light-emitting diode such as an organic light-emitting diode. The seven transistors may receive control signals using horizontal control lines. Each pixel may have first and second emission enable transistors that are coupled in series with a drive transistor and the light-emitting diode of that pixel. The first and second emission enable transistors may be coupled to a common control line or may be separately controlled so that on-bias stress can be effectively applied to the drive transistor. The display driver circuitry may have gate driver circuits that provide different gate line signals to different rows of pixels within the display. Different rows may also have different gate driver strengths and different supplemental gate line loading structures.

Abstract: A display may have an array of pixels each of which has a light-emitting diode such as an organic light-emitting diode. A drive transistor and an emission transistor may be coupled in series with the light-emitting diode of each pixel between a positive power supply and a ground power supply. The pixels may include first and second switching transistors. A data storage capacitor may be coupled between a gate and source of the drive transistor in each pixel. Signal lines may be provided in columns of pixels to route signals such as data signals, sensed drive currents from the drive transistors, and predetermined voltages between display driver circuitry and the pixels. The switching transistors, emission transistors, and drive transistors may include semiconducting-oxide transistors and silicon transistors and may be n-channel transistors or p-channel transistors.

Abstract: A system package module is provided. The system package module includes a module substrate, a plurality of first pins and a plurality of second pins. The module substrate includes a module substrate surface. The module substrate surface includes a first pin arrangement area and a second pin arrangement area. The second pin arrangement area surrounds the first pin arrangement area. The first pins are disposed in the first pin arrangement area. A first pin gap is formed between the two adjacent first pins. The second pins are disposed in the second pin arrangement area. A second pin gap is formed between the two adjacent second pins. The first pin gap is greater than the second pin gap.

Abstract: An electronic device may be provided with a display. An optical component window may be formed in the inactive area of the display. The optical component window may transmit infrared light from an infrared light source. The infrared light source may include a diffuser to allow the light source to operate in a flood illumination mode and a structured light mode. The diffuser may include liquid crystal material between first and second substrates. A sealant may surround the liquid crystal layer, and one or more spacer walls may be located between the sealant and the liquid crystal layer. An additional spacer wall may be used outside of the sealant to prevent metal from creating an electrical short between electrodes in the diffuser. Conductive material in the sealant may be used to couple a top electrode to a metal pad on a bottom substrate.

Abstract: Disclosed herein is a method comprising disposing upon a substrate a composition comprising a block copolymer; where the block copolymer comprises a first polymer and a second polymer; where the first polymer and the second polymer of the block copolymer are different from each other and the block copolymer forms a phase separated structure; an additive polymer; where the additive polymer comprises a reactive moiety that is operative to react with a substrate upon which it is disposed; and where the additive polymer comprises a homopolymer that is the chemically and structurally the same as one of the polymers in the block copolymer or where the additive polymer comprises a random copolymer that has a preferential interaction with one of the blocks of the block copolymers; and a solvent; and annealing the composition.

Abstract: A system package module is provided. The system package module includes a module substrate, a plurality of first pins and a plurality of second pins. The module substrate includes a module substrate surface. The module substrate surface includes a first pin arrangement area and a second pin arrangement area. The second pin arrangement area surrounds the first pin arrangement area. The first pins are disposed in the first pin arrangement area. A first pin gap is formed between the two adjacent first pins. The second pins are disposed in the second pin arrangement area. A second pin gap is formed between the two adjacent second pins. The first pin gap is greater than the second pin gap.

Abstract: A window may be provided with a light modulator. The light modulator may be dynamically adjusted to control visible light transmission through the window. The window may also have layers that selectively block light with non-visible wavelengths. The light-blocking layers may block ultraviolet light, near infrared light such as light from solar radiation, and far infrared light such as heat produced due to the absorption of visible light by the light modulator. The light modulator may be a guest-host liquid crystal light modulator. The guest-host liquid crystal light modulator may have a layer of liquid crystal material with dye that is interposed between polymer substrate layers. The polymer substrate layers may be thermoplastic layers that are moldable to conform to window shapes with compound curves.

Abstract: A display may have display layers such as liquid crystal display layers having a liquid crystal layer interposed between a color filter layer and a thin-film transistor layer or organic light-emitting diode layers having organic light-emitting diodes formed from thin-film transistor circuitry. The display layers may be configured to form an array of pixels that display images and may include a polarizer. An angle-of-view adjustment layer may overlap the display layers. The angle-of-view adjustment layer may include one or more liquid crystal layers. A first polarizer may be interposed between first and second liquid crystal layers and the second liquid crystal layer may be overlapped by a second polarizer. The first and second polarizers may have pass axes that are aligned with a pass axis of the polarizer in the display layers. One or more liquid crystal layers in the angle-of-view adjustment layer may include dichroic dye.