Patents by Inventor Shih-Wen Huang
Shih-Wen Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240363707Abstract: A semiconductor device is provided. The semiconductor device includes a source/drain structure, a contact structure, a glue layer, a barrier layer, and a silicide layer. The contact structure is over the source/drain structure. The glue layer surrounds the contact structure. The barrier layer is formed on at least a portion of a sidewall surface of the contact structure. The silicide layer is between the source/drain structure and the contact structure, and the silicide layer is in direct contact with the glue layer. The bottom surface of the glue layer is lower than the top surface of the source/drain structure and the bottom surface of the barrier layer.Type: ApplicationFiled: July 10, 2024Publication date: October 31, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Wen HUANG, Chung-Ting KO, Hong-Hsien KE, Chia-Hui LIN, Tai-Chun HUANG
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Patent number: 12087834Abstract: A semiconductor structure is provided. The semiconductor structure includes a gate structure, a source/drain structure, a barrier layer, and a glue layer. The gate structure is over a fin structure. The source/drain structure is in the fin structure and adjacent to the gate structure. The barrier layer is over the source/drain structure. The glue layer is adjacent to the barrier layer. The glue layer has an extending portion in direct contact with the gate structure.Type: GrantFiled: March 4, 2022Date of Patent: September 10, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Wen Huang, Chung-Ting Ko, Hong-Hsien Ke, Chia-Hui Lin, Tai-Chun Huang
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Publication number: 20240282638Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.Type: ApplicationFiled: April 16, 2024Publication date: August 22, 2024Inventors: Shih-Wen Huang, Jaming Chang, Kai Hung Cheng, Chia-Hui Lin, Jei Ming Chen
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Patent number: 11990375Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.Type: GrantFiled: June 29, 2022Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Wen Huang, Jaming Chang, Kai Hung Cheng, Chia-Hui Lin, Jei Ming Chen
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Publication number: 20230260896Abstract: A device package including an interposer. The interposer comprising: a semiconductor substrate; first through vias extending through the semiconductor substrate; an interconnect structure comprising: a first metallization pattern in an inorganic insulating material; and a passivation film over the first metallization pattern; and a first redistribution structure over the passivation film. The first redistribution structure comprising a second metallization pattern in an organic insulating material. The device package further including an integrated circuit die over and attached to the interposer; and a first encapsulant around the integrated circuit die.Type: ApplicationFiled: June 10, 2022Publication date: August 17, 2023Inventors: Hsien-Pin Hu, Shang-Yun Hou, Shih-Wen Huang
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Publication number: 20220328360Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.Type: ApplicationFiled: June 29, 2022Publication date: October 13, 2022Inventors: Shih-Wen Huang, Jaming Chang, Kai Hung Cheng, Chia-Hui Lin, Jei Ming Chen
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Patent number: 11380593Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.Type: GrantFiled: September 14, 2020Date of Patent: July 5, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Wen Huang, Jaming Chang, Kai Hung Cheng, Chia-Hui Lin, Jei Ming Chen
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Publication number: 20220190127Abstract: A semiconductor structure is provided. The semiconductor structure includes a gate structure, a source/drain structure, a barrier layer, and a glue layer. The gate structure is over a fin structure. The source/drain structure is in the fin structure and adjacent to the gate structure. The barrier layer is over the source/drain structure. The glue layer is adjacent to the barrier layer. The glue layer has an extending portion in direct contact with the gate structure.Type: ApplicationFiled: March 4, 2022Publication date: June 16, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Wen HUANG, Chung-Ting KO, Hong-Hsien KE, Chia-Hui LIN, Tai-Chun HUANG
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Patent number: 11296198Abstract: A method for forming a semiconductor structure is provided. The method includes forming a gate structure over a fin structure, forming a source/drain structure in the fin structure and adjacent to the gate structure, forming a dielectric layer over the gate structure and the source/drain structure, and forming an opening in the dielectric layer to expose the source/drain structure. The method further includes depositing a barrier layer lining a sidewall surface of the opening and a top surface of the source/drain structure. The method further includes etching a portion of the barrier layer to expose the source/drain structure. The method further includes depositing a glue layer covering the sidewall surface of the opening and the source/drain structure in the opening. The method further includes forming a contact structure filling the opening in the dielectric layer. The contact structure is surrounded by the glue layer.Type: GrantFiled: April 2, 2020Date of Patent: April 5, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Wen Huang, Chung-Ting Ko, Hong-Hsien Ke, Chia-Hui Lin, Tai-Chun Huang
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Publication number: 20210361706Abstract: Combined therapy of cancer (e.g., breast cancer) involving a cyclophosphamide compound and natural killer (NK) cells. Also provided herein are methods for inducing immune memory and/or reducing the risk of tumor recurrence using the combined therapy of a cyclophosphamide compound and NK cells.Type: ApplicationFiled: August 28, 2019Publication date: November 25, 2021Applicant: ACADEMIA SINICAInventors: Nan-Shih LIAO, Shih-Wen HUANG, Zhen-Qi WU, Yein-Gei LAI, Yae-Huei LIOU
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Patent number: 11183399Abstract: An interposer substrate is manufactured with a scribe line between adjacent regions. In an embodiment a separate exposure reticle is utilized to pattern the scribe line. The exposure reticle to pattern the scribe line will create an exposure region which overlaps and overhangs the exposure regions utilized to form adjacent regions.Type: GrantFiled: September 30, 2019Date of Patent: November 23, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Hsin Wei, Hsien-Pin Hu, Shang-Yun Hou, Chi-Hsi Wu, Chen-Hua Yu, Wen-Jung Chuang, Chun-Che Chen, Jhih-Ming Lin, Chih-Ching Lin, Shih-Wen Huang, Chun Hua Chang, Tsung-Yang Hsieh
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Patent number: 11101140Abstract: An interposer substrate is manufactured with a scribe line between adjacent regions. In an embodiment a separate exposure reticle is utilized to pattern the scribe line. The exposure reticle to pattern the scribe line will create an exposure region which overlaps and overhangs the exposure regions utilized to form adjacent regions.Type: GrantFiled: August 1, 2018Date of Patent: August 24, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Hsin Wei, Hsien-Pin Hu, Shang-Yun Hou, Chi-Hsi Wu, Chen-Hua Yu, Wen-Jung Chuang, Chun-Che Chen, Jhih-Ming Lin, Chih-Ching Lin, Shih-Wen Huang, Chun Hua Chang, Tsung-Yang Hsieh
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Patent number: 11049945Abstract: Semiconductor device structures and methods for forming the same are provided. A semiconductor device structure includes a gate structure over a semiconductor substrate. The gate structure includes a gate electrode layer and a gate dielectric layer covering a bottom surface and sidewalls of the gate electrode layer. The semiconductor device structure also includes spacer elements in contact with sidewalls of the gate structure and protruding from a top surface of the gate electrode layer. The semiconductor device structure also includes a first protection layer over the gate electrode layer and between the spacer elements. The semiconductor device structure also includes a dielectric layer over the first protection layer and between the spacer elements. A portion of the dielectric layer is between sidewalls of the spacer elements and sidewalls of the first protection layer.Type: GrantFiled: April 29, 2019Date of Patent: June 29, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Wen Huang, Yun-Wen Chu, Hong-Hsien Ke, Chia-Hui Lin, Shin-Yeu Tsai, Shih-Chieh Chang
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Publication number: 20200411386Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.Type: ApplicationFiled: September 14, 2020Publication date: December 31, 2020Inventors: Shih-Wen Huang, Jaming Chang, Kai Hung Cheng, Chia-Hui Lin, Jei Ming Chen
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Publication number: 20200357612Abstract: A method of wafer processing includes supporting a wafer in a process chamber. The method further includes introducing a flow of a gaseous material through an inlet of the process chamber to process the wafer. The method further includes generating, between the inlet and the wafer, controllable forces acting in various directions on the gaseous material to spread the gaseous material inside the process chamber.Type: ApplicationFiled: July 24, 2020Publication date: November 12, 2020Inventors: Chien Kuo HUANG, Shih-Wen HUANG, Joung-Wei LIOU, Chia-I SHEN, Fei-Fan CHEN
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Patent number: 10777466Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.Type: GrantFiled: March 15, 2018Date of Patent: September 15, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Wen Huang, Chia-Hui Lin, Jaming Chang, Jei Ming Chen, Kai Hung Cheng
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Patent number: 10741366Abstract: A wafer process chamber includes a wafer support in the wafer process chamber, the wafer support configured to support a wafer. The process chamber includes a gas diffuser unit within the wafer process chamber. The gas diffuser unit includes at least one controllable diffuser configured to generate one or more controllable forces acting in various directions on a gaseous material in a flow of the gaseous material introduced into the process chamber, to spread the gaseous material inside the process chamber. The gas diffuser unit includes a power source coupled to the at least one controllable diffuser, the power source configured to supply power to the at least one controllable diffuser to generate the one or more controllable forces. The gas diffuser unit includes a controller coupled to the power source, the controller configured to control the power supplied by the power source to the at least one controllable diffuser.Type: GrantFiled: June 25, 2018Date of Patent: August 11, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien Kuo Huang, Shih-Wen Huang, Joung-Wei Liou, Chia-I Shen, Fei-Fan Chen
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Publication number: 20200235214Abstract: A method for forming a semiconductor structure is provided. The method includes forming a gate structure over a fin structure, forming a source/drain structure in the fin structure and adjacent to the gate structure, forming a dielectric layer over the gate structure and the source/drain structure, and forming an opening in the dielectric layer to expose the source/drain structure. The method further includes depositing a barrier layer lining a sidewall surface of the opening and a top surface of the source/drain structure. The method further includes etching a portion of the barrier layer to expose the source/drain structure. The method further includes depositing a glue layer covering the sidewall surface of the opening and the source/drain structure in the opening. The method further includes forming a contact structure filling the opening in the dielectric layer. The contact structure is surrounded by the glue layer.Type: ApplicationFiled: April 2, 2020Publication date: July 23, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Wen HUANG, Chung-Ting KO, Hong-Hsien KE, Chia-Hui LIN, Tai-Chun HUANG
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Patent number: 10720430Abstract: A method includes etching a semiconductor substrate to form trenches, with a portion of the semiconductor substrate between the trenches being a semiconductor strip, and depositing a dielectric dose film on sidewalls of the semiconductor strip. The dielectric dose film is doped with a dopant of n-type or p-type. The remaining portions of the trenches are filled with a dielectric material. A planarization is performed on the dielectric material. Remaining portions of the dielectric dose film and the dielectric material form Shallow Trench Isolation (STI) regions. A thermal treatment is performed to diffuse the dopant in the dielectric dose film into the semiconductor strip.Type: GrantFiled: December 26, 2019Date of Patent: July 21, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Wen Huang, Chia-Hui Lin, Shin-Yeu Tsai, Kai Hung Cheng
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Publication number: 20200144258Abstract: A method includes etching a semiconductor substrate to form trenches, with a portion of the semiconductor substrate between the trenches being a semiconductor strip, and depositing a dielectric dose film on sidewalls of the semiconductor strip. The dielectric dose film is doped with a dopant of n-type or p-type. The remaining portions of the trenches are filled with a dielectric material. A planarization is performed on the dielectric material. Remaining portions of the dielectric dose film and the dielectric material form Shallow Trench Isolation (STI) regions. A thermal treatment is performed to diffuse the dopant in the dielectric dose film into the semiconductor strip.Type: ApplicationFiled: December 26, 2019Publication date: May 7, 2020Inventors: Shih-Wen Huang, Chia-Hui Lin, Shin-Yeu Tsai, Kai Hung Cheng