Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.

Abstract: A common mode filter includes a first iron core, a second iron core, a first coil, and a second coil. The first iron core includes two first electrode portions and two second electrode portions. The second iron core is disposed above the first iron core, and the first iron core and the second iron core are adhered to each other. All surfaces of the second iron core are coated with an insulating layer. The first coil is wound around the first iron core and the second iron core. The second coil is wound around the first iron core and the second iron core.

Abstract: A method and apparatus of prediction for video coding are disclosed. According to one method, a luma Intra prediction mode is determined for a corresponding luma block collocated with the current chroma block, where a predefined mode is assigned to the luma Intra prediction mode when the corresponding luma block collocated with the current chroma block satisfies one or more conditions. A chroma Intra prediction mode is determined for the current chroma block according to the luma Intra prediction mode. The current chroma block is then encoded or decoded according to the chroma Intra prediction mode. According to another method, a predefined mode is assigned to Intra prediction mode for the current block when the current block satisfies one or more conditions. The current block is then encoded or decoded according to the Intra prediction mode.

Abstract: An interconnect fabrication method is disclosed herein that utilizes a disposable etch stop hard mask over a gate structure during source/drain contact formation and replaces the disposable etch stop hard mask with a dielectric feature (in some embodiments, dielectric layers having a lower dielectric constant than a dielectric constant of dielectric layers of the disposable etch stop hard mask) before gate contact formation. An exemplary device includes a contact etch stop layer (CESL) having a first sidewall CESL portion and a second sidewall CESL portion separated by a spacing and a dielectric feature disposed over a gate structure, where the dielectric feature and the gate structure fill the spacing between the first sidewall CESL portion and the second sidewall CESL portion. The dielectric feature includes a bulk dielectric over a dielectric liner. The dielectric liner separates the bulk dielectric from the gate structure and the CESL.

Abstract: A semiconductor device structure includes nanostructures formed over a substrate. The structure also includes a gate structure formed over and around the nanostructures. The structure also includes a spacer layer formed over a sidewall of the gate structure over the nanostructures. The structure also includes a source/drain epitaxial structure formed adjacent to the spacer layer. The structure also includes a contact structure formed over the source/drain epitaxial structure with an air spacer formed between the spacer layer and the contact structure.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain region formed in a semiconductor substrate, a source/drain contact structure formed over the source/drain region, and a silicide region formed between the source/drain region and the source/drain contact structure. The semiconductor device structure also includes a first insulating spacer surrounding and in direct contact with the source/drain contact structure and a second insulating spacer and a third insulating spacer respectively formed on two opposite sidewalls of the source/drain contact structure and in direct contact with an outer edge of the first insulating spacer. A first sidewall of the second insulating spacer and a second sidewall of the third insulating spacer are respectively aligned to two opposite side edges of the source/drain region.

Abstract: A semiconductor device is provided. The semiconductor device includes a source/drain structure, a contact structure, a glue layer, a barrier layer, and a silicide layer. The contact structure is over the source/drain structure. The glue layer surrounds the contact structure. The barrier layer is formed on at least a portion of a sidewall surface of the contact structure. The silicide layer is between the source/drain structure and the contact structure, and the silicide layer is in direct contact with the glue layer. The bottom surface of the glue layer is lower than the top surface of the source/drain structure and the bottom surface of the barrier layer.

Abstract: One aspect of the present disclosure pertains to a method of forming a semiconductor device. The method includes forming a gate stack over a channel region and forming a first source/drain (S/D) trench adjacent the channel region and extending into the substrate below a top surface of an isolation structure. The method includes forming a first epitaxial S/D feature in the first S/D trench and forming a first frontside metal contact over the first epitaxial S/D feature. The method further includes forming a first backside trench that exposes a bottom surface of the first epitaxial S/D feature and forming a first backside conductive feature in the first backside trench and on the exposed bottom surface of the first epitaxial S/D feature. A top surface of the first backside conductive feature is under a bottommost surface of the gate stack.

Abstract: A side by side image detection method and an electronic apparatus using the same are provided. The side by side image detection method includes the following steps. A first image with a first image size is obtained. A second image with a second image size that conforms to a side-by-side image format is detected within the first image by using a convolutional neural network model.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.

Abstract: A work function metal gate device includes a gate, a drift region, a source, a drain and a first isolation structure. The gate includes a convex stair-shaped work function metal stack or a concave stair-shaped work function metal stack disposed on a substrate. The drift region is disposed in the substrate below a part of the gate. The source is located in the substrate and the drain is located in the drift region beside the gate. The first isolation structure is disposed in the drift region between the gate and the drain.

Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to associated semiconducting oxide transistors. The semiconducting oxide transistors may exhibit different device characteristics. Some of the semiconducting oxide transistors may be formed using a first oxide layer formed from a first semiconducting oxide material using first processing steps, whereas other semiconducting oxide transistors are formed using a second oxide layer formed from a second semiconducting oxide material using second processing steps different than the first processing steps. The display may include three or more different semiconducting oxide layers formed during different processing steps.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a gate structure, a source/drain structure, a barrier layer, and a glue layer. The gate structure is over a fin structure. The source/drain structure is in the fin structure and adjacent to the gate structure. The barrier layer is over the source/drain structure. The glue layer is adjacent to the barrier layer. The glue layer has an extending portion in direct contact with the gate structure.

Abstract: A method of defining a pattern includes forming a plurality of cut shapes and a first plurality of openings within a first layer of a multi-layer hard mask to expose first portions of the second layer. A plurality of etch stops is formed by implanting an etch rate modifying species in a portion of the plurality of cut shapes. The first layer is directionally etched at the plurality of cut shapes such that the plurality of etch stops remain. A spacer layer is formed on the first layer and the first portions. A second plurality of openings is formed within the spacer layer to expose second portions of the second layer. The spacer layer is directionally etched to remove the spacer layer from sidewalls of the plurality of etch stops. Portions of the second layer exposed through the first plurality of openings and the second plurality of openings are etched.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain region formed in a semiconductor substrate, a source/drain contact structure formed over the source/drain region, and a gate electrode layer formed adjacent to the source/drain contact structure. The semiconductor device structure also includes a first spacer and a second spacer laterally and successively arranged from the sidewall of the gate electrode layer to the sidewall of the source/drain contact structure. The semiconductor device structure further includes a silicide region formed in the source/drain region. The top width of the silicide region is greater than the bottom width of the source/drain contact structure and less than the top width of the source/drain region.

Abstract: Video processing methods and apparatuses in a video encoding or decoding system. A method receives input data associated with a current block in a current picture, determines if the current block is an out-of-bounds node, wherein the out-of-bounds node is a coding tree node of the current picture with a block region across a current picture boundary, and determines whether the current block is larger than a predefined size. The method further determines an inferred splitting type if the current block is an out-of-bounds node and the current block is larger than the predefined size and applies the inferred splitting type to split the current block into child blocks if the current block is an out-of-bounds node and the current block is larger than the predefined size, and then adaptively splitting each child block into one or more leaf blocks.

Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.

Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.

Abstract: A device package including an interposer. The interposer comprising: a semiconductor substrate; first through vias extending through the semiconductor substrate; an interconnect structure comprising: a first metallization pattern in an inorganic insulating material; and a passivation film over the first metallization pattern; and a first redistribution structure over the passivation film. The first redistribution structure comprising a second metallization pattern in an organic insulating material. The device package further including an integrated circuit die over and attached to the interposer; and a first encapsulant around the integrated circuit die.