Patents by Inventor Shih-Yen Chiu

Shih-Yen Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10031574
    Abstract: A computing system includes a multi-core processor and a core controller. The core controller is for: monitoring utilization of the multi-core processor; calculating a target performance index according to the utilization of the multi-core processor, a target utilization and a first performance index, wherein the first performance index is associated with a first entry of a dynamic voltage frequency scaling (DVFS) table that corresponds to a current setting for the multi-core processor; and selecting a second entry of the DVFS table that corresponds to a target-setting according to the target performance index and a second performance index that is associated with the second entry. The target-setting is used to configure the multi-core processor.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: July 24, 2018
    Assignee: MEDIATEK INC.
    Inventors: Jih-Ming Hsu, Yen-Lin Lee, Jia-Ming Chen, Shih-Yen Chiu, Chung-Ho Chang, Ya-Ting Chang, Ming-Hsien Lee
  • Patent number: 9977699
    Abstract: A multi-cluster system having processor cores of different energy efficiency characteristics is configured to operate with high efficiency such that performance and power requirements can be satisfied. The system includes multiple processor cores in a hierarchy of groups. The hierarchy of groups includes: multiple level-1 groups, each level-1 group including one or more of processor cores having identical energy efficiency characteristics, and each level-1 group configured to be assigned tasks by a level-1 scheduler; one or more level-2 groups, each level-2 group including respective level-1 groups, the processor cores in different level-1 groups of the same level-2 group having different energy efficiency characteristics, and each level-2 group configured to be assigned tasks by a respective level-2 scheduler; and a level-3 group including the one or more level-2 groups and configured to be assigned tasks by a level-3 scheduler.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: May 22, 2018
    Assignee: MediaTek, Inc.
    Inventors: Jia-Ming Chen, Hung-Lin Chou, Ya-Ting Chang, Shih-Yen Chiu, Chia-Hao Hsu, Yu-Ming Lin, Wan-Ching Huang, Jen-Chieh Yang, Pi-Cheng Hsiao
  • Publication number: 20170322616
    Abstract: Methods and apparatus are provided for adaptive optimization of low-power strategies. In one novel aspect, the device monitors one or more thermal-performance parameters and determines a plurality of operation scenarios for a plurality of corresponding low-power policies. Based on corresponding operation scenarios, the device selects corresponding low-power policy. The device applies different low-power strategy for temperature control based on low-power policies. Different low-power policy is applied to different low-power techniques, such as the DVFS, the CPU hot-plug, and the task migration. In another novel aspect, the device obtains one or more user-defined policy for each corresponding low-power technique. The selection of each low-power policy is further based on its corresponding user-defined policy. In one embodiment, the user-defined DVFS policy includes power policy, performance policy, and DVFS-balanced policy.
    Type: Application
    Filed: May 6, 2016
    Publication date: November 9, 2017
    Inventors: Kuo-Su Hsiao, Yen-Lin Lee, Shih-Yen Chiu, Jia-Ming Chen, Mark Shane Peng, Ya-Ting Chang
  • Publication number: 20170160962
    Abstract: A multicore processor system includes multiple processor cores. When a processor core goes offline, the offline processor core is mapped to a mapped processor core, which is selected from an emulated processor core and one or more online processor cores among the multiple processor cores. The emulated processor core is a software construct containing an emulated state of the offline processor core. When the multicore processor system receives a system call that is sent from a requestor to the offline processor core to request for system information from the offline processor core, the system call is re-directed to the mapped processor core. The system information is returned from the mapped processor core to the requestor in response to the system call.
    Type: Application
    Filed: November 29, 2016
    Publication date: June 8, 2017
    Inventors: Shih-Yen Chiu, Wan-Ching Huang, Chung-Ho Chang, Ya-Ting Chang, Ming-Ju Wu, Nicholas Ching Hui Tang
  • Patent number: 9665161
    Abstract: A method and a computer-readable medium for dynamically managing power of a multi-core processor of a computing system are provided. The multi-core processor generates a dynamic voltage and frequency scaling (DVFS) table, determines a first index by alternatively selecting either a power budget or a required performance thereof, determines a current thread level parallelism (TLP) of the computing system, selects one of entries according to the current TLP and the first index, and configure first cores and second cores thereof according to a first settings and a second settings of the selected entry.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: May 30, 2017
    Assignee: MEDIATEK INC.
    Inventors: Jih-Ming Hsu, Wen-Tsan Hsieh, Che-Ming Hsu, Yeh-Ji Chou, Jen-Chieh Yang, Shih-Yen Chiu, Wan-Ching Huang, Ming-Hsien Lee
  • Publication number: 20160342198
    Abstract: A computing system includes a multi-core processor and a core controller. The core controller is for: monitoring utilization of the multi-core processor; calculating a target performance index according to the utilization of the multi-core processor, a target utilization and a first performance index, wherein the first performance index is associated with a first entry of a dynamic voltage frequency scaling (DVFS) table that corresponds to a current setting for the multi-core processor; and selecting a second entry of the DVFS table that corresponds to a target-setting according to the target performance index and a second performance index that is associated with the second entry. The target-setting is used to configure the multi-core processor.
    Type: Application
    Filed: September 4, 2015
    Publication date: November 24, 2016
    Inventors: Jih-Ming HSU, Yen-Lin LEE, Jia-Ming CHEN, Shih-Yen CHIU, Chung-Ho CHANG, Ya-Ting CHANG, Ming-Hsien LEE
  • Publication number: 20160327999
    Abstract: A computing system with multiple processor cores manages power and performance by dynamic frequency scaling. The system detects a condition when a total number of active processor cores within one or more clusters is less than a predetermined number, and an operating frequency of the active processor cores has risen to a specified highest frequency. The system also obtains ambient temperature measurement of the one or more clusters. Upon detecting the condition, the system increases the operating frequency above the specified highest frequency based on the ambient temperature measurement while maintaining a same level of supply voltage to the active processor cores.
    Type: Application
    Filed: September 17, 2015
    Publication date: November 10, 2016
    Inventors: Ya-Ting CHANG, Lee-Kee YONG, Shih-Yen CHIU, Ming-Hsien LEE, Jia-Ming CHEN, Yu-Ming LIN, Hung-Lin CHOU, Tzu-Jen LO, Koon Woon SOON
  • Publication number: 20160314024
    Abstract: A computing system supports a clearance mode for its processor cores. The computing system can transition a target processor core from an active mode into a clearance mode according to a system policy. The system policy determines the number of processor cores to be in the active mode. The transitioning into the clearance mode includes the operations of migrating work from the target processor core to one or more other processor cores in the active mode in the computing system; and removing the target processor core from a scheduling configuration of the computing system to prevent task assignment to the target processor core. When the target processor core is in the clearance mode, the target processor core is maintained in an online idle state in which the target processor core performs no work.
    Type: Application
    Filed: April 14, 2016
    Publication date: October 27, 2016
    Inventors: Ya-Ting Chang, Ming-Ju Wu, Pi-Cheng Chen, Jia-Ming Chen, Chung-Ho Chang, Pi-Cheng Hsiao, Hung-Lin Chou, Shih-Yen Chiu
  • Publication number: 20160139964
    Abstract: A multi-cluster system having processor cores of different energy efficiency characteristics is configured to operate with high efficiency such that performance and power requirements can be satisfied. The system includes multiple processor cores in a hierarchy of groups. The hierarchy of groups includes: multiple level-1 groups, each level-1 group including one or more of processor cores having identical energy efficiency characteristics, and each level-1 group configured to be assigned tasks by a level-1 scheduler; one or more level-2 groups, each level-2 group including respective level-1 groups, the processor cores in different level-1 groups of the same level-2 group having different energy efficiency characteristics, and each level-2 group configured to be assigned tasks by a respective level-2 scheduler; and a level-3 group including the one or more level-2 groups and configured to be assigned tasks by a level-3 scheduler.
    Type: Application
    Filed: November 10, 2015
    Publication date: May 19, 2016
    Inventors: Jia-Ming CHEN, Hung-Lin CHOU, Ya-Ting CHANG, Shih-Yen CHIU, Chia-Hao HSU, Yu-Ming LIN, Wan-Ching HUANG, Jen-Chieh YANG, Pi-Cheng HSIAO
  • Publication number: 20160062447
    Abstract: A method and a computer-readable medium for dynamically managing power of a multi-core processor of a computing system are provided. The multi-core processor generates a dynamic voltage and frequency scaling (DVFS) table, determines a first index by alternatively selecting either a power budget or a required performance thereof, determines a current thread level parallelism (TLP) of the computing system, selects one of entries according to the current TLP and the first index, and configure first cores and second cores thereof according to a first settings and a second settings of the selected entry.
    Type: Application
    Filed: July 29, 2015
    Publication date: March 3, 2016
    Inventors: Jih-Ming Hsu, Wen-Tsan Hsieh, Che-Ming Hsu, Yeh-Ji Chou, Jen-Chieh Yang, Shih-Yen Chiu, Wan-Ching Huang, Ming-Hsien Lee