Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.

Abstract: A flyback power converter includes a power transformer, a first lossless voltage conversion circuit, a first low-dropout linear regulator and a secondary side power supply circuit. The first low-dropout linear regulator (LDO) generates a first operation voltage as power supply for being supplied to a sub-operation circuit. The secondary side power supply circuit includes a second lossless voltage conversion circuit and a second LDO. The second LDO generates a second operation voltage. The first operation voltage and the second operation voltage are shunted to a common node. When a first lossless conversion voltage is greater than a first threshold voltage, the second LDO is enabled to generate the second operation voltage to replace the first operation voltage as power supply supplied to the sub-operation circuit; wherein the second lossless conversion voltage is lower than the first lossless switching voltage.

Abstract: A link down detector and a link down detecting method for Ethernet are provided. The link down detecting method includes the following steps. Firstly, a received signal is received, and a high-frequency band signal is extracted from the received signal. Consequently, the high-frequency band signal is formed as an extraction signal. Then, a high-frequency band power value of the extraction signal is calculated, and a full band power value of the received signal is calculated. Then, a ratio value of the high-frequency band power value to the full band power value is calculated. In a link up status, if the ratio value is changed dramatically in a specified time, a link down signal is asserted to indicate that a network device connected to the Ethernet is switched to a link down status.

Abstract: The present invention discloses a respiratory mask to connect a user and a breathing tube for receiving a first gas and releasing a second gas, so as to provide an user's respiratory system to exchange gas. It comprises a main part, an air chamber exchange part, an insert and a clamping part. The main part provides a first, second, and third openings that are communicated each other. The first opening connects to the breathing tube to receive the first gas from the breathing tube. The air chamber exchange part provides an exhaust assembly to relieve pressure according to an internal air pressure of the air chamber exchange part. The insert connects to the user's nose so as to direct the first gas to the user or direct the second gas from the user to the air chamber exchange part. The clamping part connects to the user's mouth.

Abstract: A semiconductor device is described. An isolation region is disposed on the substrate. A plurality of channels extend through the isolation region from the substrate. The channels including an active channel and an inactive channel. A dummy fin is disposed on the isolation region and between the active channel and the inactive channel. An active gate is disposed over the active channel and the inactive channel, and contacts the isolation region. A dielectric material extends through the active gate and contacts a top of the dummy fin. The inactive channel is a closest inactive channel to the dielectric material. A long axis of the active channel extends in a first direction. A long axis of the active gate extends in a second direction. The active channel extends in a third direction from the substrate. The dielectric material is closer to the inactive channel than to the active channel.

Abstract: The present invention discloses a respiratory mask to connect a user and a breathing tube for receiving a first gas and releasing a second gas, so as to provide an user's respiratory system to exchange gas. It comprises a main part, an air chamber exchange part, an insert and a clamping part. The main part provides a first, second, and third openings that are communicated each other. The first opening connects to the breathing tube to receive the first gas from the breathing tube. The air chamber exchange part provides an exhaust assembly to relieve pressure according to an internal air pressure of the air chamber exchange part. The insert connects to the user's nose so as to direct the first gas to the user or direct the second gas from the user to the air chamber exchange part. The clamping part connects to the user's mouth.

Abstract: This present invention provides a chip scale sensing chip package, comprising: a sensing chip with a first top surface and a first bottom surface opposite to each other, comprising: a sensing device adjacent to the first top surface; and a plurality of conductive pads adjacent to first top surface and the sensing device; a wiring layer formed on the first bottom surface and connected to each of the conductive pads; a dam having a supporter with a first opening and a spacer with a second opening formed on the first top surface, wherein the supporter is within the second opening and adjacent to the spacer, and the spacer is higher than the supporter by a predetermined distance d; a lens formed on the first top surface exposed by the first opening and above the sensing device; and an optical filter deposed on the supporter and above the lens.

Abstract: A chip package includes a chip, a laser stop layer, a first through hole, an isolation layer, a second through hole and a conductive layer. The laser stop layer is disposed above a first surface of the chip, and the first through hole is extended from a second surface to the first surface of the chip to expose the laser stop layer. The isolation layer is below the second surface and in the first through hole, and the isolation layer has a third surface opposite to the second surface. The second through hole is extended from the third surface to the first surface, and the second through hole is through the first through hole to expose the laser stop layer. The conductive layer is disposed below the third surface and extended into the second through hole to contact the laser stop layer.

Abstract: A chip package included a chip, a first though hole, a laser stop structure, a first isolation layer, a second though hole and a conductive layer. The first though hole is extended from the second surface to the first surface of the chip to expose a conductive pad, and the laser stop structure is disposed on the conductive pad exposed by the first through hole, which an upper surface of the laser stop structure is above the second surface. The first isolation layer covers the second surface and the laser stop structure, and the first isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the second surface to expose the laser stop structure, and a conductive layer is on the third surface and extended into the second though hole to contact the laser stop structure.

Abstract: A chip package includes a chip, a laser stopper, an isolation layer, a redistribution layer, an insulating layer, and a conductive structure. The chip has a conductive pad, a first surface, and a second surface opposite to the first surface. The conductive pad is located on the first surface. The second surface has a first though hole to expose the conductive pad. The laser stopper is located on the conductive pad. The isolation layer is located on the second surface and in the first though hole. The isolation layer has a third surface opposite to the second surface. The isolation layer and the conductive pad have a second though hole together, such that the laser stopper is exposed through the second though hole. The redistribution layer is located on the third surface, the sidewall of the second though hole, and the laser stopper.

Abstract: A chip package includes a chip, a laser stopper, an isolation layer, a redistribution layer, an insulating layer, and a conductive structure. The chip has a conductive pad, a first surface, and a second surface. The conductive pad is located on the first surface. The second surface has a first through hole to expose the conductive pad. The laser stopper is located on the conductive pad in the first through hole. The isolation layer is located on the second surface and in the first through hole. The isolation layer has a third surface opposite to the second surface, and has a second through hole to expose the laser stopper. The redistribution layer is located on the third surface, a sidewall of the second through hole, and the laser stopper in the second through hole. The conductive structure is located on the redistribution.

Abstract: This present invention provides a chip scale sensing chip package, comprising: a sensing chip with a first top surface and a first bottom surface opposite to each other, comprising: a sensing device adjacent to the first top surface; and a plurality of conductive pads adjacent to first top surface and the sensing device; a wiring layer formed on the first bottom surface and connected to each of the conductive pads; a dam having a supporter with a first opening and a spacer with a second opening formed on the first top surface, wherein the supporter is within the second opening and adjacent to the spacer, and the spacer is higher than the supporter by a predetermined distance d; a lens formed on the first top surface exposed by the first opening and above the sensing device; and an optical filter deposed on the supporter and above the lens.

Abstract: A chip package included a chip, a first though hole, a laser stop structure, a first isolation layer, a second though hole and a conductive layer. The first though hole is extended from the second surface to the first surface of the chip to expose a conductive pad, and the laser stop structure is disposed on the conductive pad exposed by the first through hole, which an upper surface of the laser stop structure is above the second surface. The first isolation layer covers the second surface and the laser stop structure, and the first isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the second surface to expose the laser stop structure, and a conductive layer is on the third surface and extended into the second though hole to contact the laser stop structure.

Abstract: A chip package includes a chip, a laser stopper, an isolation layer, a redistribution layer, an insulating layer, and a conductive structure. The chip has a conductive pad, a first surface, and a second surface opposite to the first surface. The conductive pad is located on the first surface. The second surface has a first though hole to expose the conductive pad. The laser stopper is located on the conductive pad. The isolation layer is located on the second surface and in the first though hole. The isolation layer has a third surface opposite to the second surface. The isolation layer and the conductive pad have a second though hole together, such that the laser stopper is exposed through the second though hole. The redistribution layer is located on the third surface, the sidewall of the second though hole, and the laser stopper.

Abstract: A chip package included a chip, a first though hole, a laser stop structure, a first isolation layer, a second though hole and a conductive layer. The first though hole is extended from the second surface to the first surface of the chip to expose a conductive pad, and the laser stop structure is disposed on the conductive pad exposed by the first through hole, which an upper surface of the laser stop structure is above the second surface. The first isolation layer covers the second surface and the laser stop structure, and the first isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the second surface to expose the laser stop structure, and a conductive layer is on the third surface and extended into the second though hole to contact the laser stop structure.

Abstract: A chip package includes a chip, a laser stopper, an isolation layer, a redistribution layer, an insulating layer, and a conductive structure. The chip has a conductive pad, a first surface, and a second surface opposite to the first surface. The conductive pad is located on the first surface. The second surface has a first though hole to expose the conductive pad. The laser stopper is located on the conductive pad. The isolation layer is located on the second surface and in the first though hole. The isolation layer has a third surface opposite to the second surface. The isolation layer and the conductive pad have a second though hole together, such that the laser stopper is exposed through the second though hole. The redistribution layer is located on the third surface, the sidewall of the second though hole, and the laser stopper.

Abstract: A chip package includes a chip, a laser stop layer, a first though hole, an isolation layer, a second though hole and a conductive layer. The laser stop layer is disposed above a first surface of the chip, and the first though hole is extended from a second surface to the first surface of the chip to expose the laser stop layer. The isolation layer is below the second surface and in the first through hole, and the isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the first surface, and the second though hole is through the first through hole to expose the laser stop layer. The conductive layer is disposed below the third surface and extended into the second though hole to contact the laser stop layer.

Abstract: A chip package including a chip, a first though hole, a conductive structure, a first isolation layer, a second though hole and a first conductive layer. The first though hole is extended from a second surface to a first surface to expose a conductive pad, and the conductive structure is on the second surface and extended to the first though hole to contact the conductive pad. The conductive structure includes a second conductive layer and a laser stopper. The first isolation layer is on the second surface and covering the conductive structure, and the first isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the second surface to expose the laser stopper, and the first conductive layer is on the third surface and extended to the second though hole to contact the laser stopper.

Abstract: A chip package included a chip, a first though hole, a laser stop structure, a first isolation layer, a second though hole and a conductive layer. The first though hole is extended from the second surface to the first surface of the chip to expose a conductive pad, and the laser stop structure is disposed on the conductive pad exposed by the first through hole, which an upper surface of the laser stop structure is above the second surface. The first isolation layer covers the second surface and the laser stop structure, and the first isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the second surface to expose the laser stop structure, and a conductive layer is on the third surface and extended into the second though hole to contact the laser stop structure.

Abstract: A chip package includes a chip, a laser stopper, an isolation layer, a redistribution layer, an insulating layer, and a conductive structure. The chip has a conductive pad, a first surface, and a second surface. The conductive pad is located on the first surface. The second surface has a first though hole to expose the conductive pad. The laser stopper is located on the conductive pad in the first though hole. The isolation layer is located on the second surface and in the first though hole. The isolation layer has a third surface opposite to the second surface, and has a second though hole to expose the laser stopper. The redistribution layer is located on the third surface, a sidewall of the second though hole, and the laser stopper in the second though hole. The conductive structure is located on the redistribution.