Patents by Inventor Shih-Yi Syu

Shih-Yi Syu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190267305
    Abstract: A die includes a semiconductor substrate, a through-via penetrating through the semiconductor substrate, a seal ring overlying and connected to the through-via, and an electrical connector underlying the semiconductor substrate and electrically coupled to the seal ring through the through-via.
    Type: Application
    Filed: May 13, 2019
    Publication date: August 29, 2019
    Inventors: Jing-Cheng Lin, Shih-Yi Syu
  • Patent number: 10290559
    Abstract: A die includes a semiconductor substrate, a through-via penetrating through the semiconductor substrate, a seal ring overlying and connected to the through-via, and an electrical connector underlying the semiconductor substrate and electrically coupled to the seal ring through the through-via.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Shih-Yi Syu
  • Patent number: 10224287
    Abstract: An RDL structure on a passivation layer includes a first landing pad disposed directly above a first on-chip metal pad; a first via in a passivation layer to electrically connect the first landing pad with the first on-chip metal pad; a second landing pad disposed directly above the second on-chip metal pad; a second via in the passivation layer to electrically connect the second landing pad with the second on-chip metal pad; and at least five traces being disposed on the passivation layer and passing through a space between the first landing pad and the second landing pad.
    Type: Grant
    Filed: June 3, 2017
    Date of Patent: March 5, 2019
    Assignee: MediaTek Inc.
    Inventors: Shih-Yi Syu, Tung-Hsien Hsieh, Che-Ya Chou
  • Publication number: 20180082936
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first carrier substrate having a first surface and an opposing second surface. A second carrier substrate is stacked on the first carrier substrate and has a first surface and an opposing second surface that faces the first surface of the first carrier substrate. A semiconductor die is mounted on the first surface of the second carrier substrate. A heat spreader is disposed on the first surface of the first carrier substrate to cover and surround the second carrier substrate and the semiconductor die. A method for forming the semiconductor package structure is also provided.
    Type: Application
    Filed: September 11, 2017
    Publication date: March 22, 2018
    Inventors: Shih-Yi SYU, Chia-Yu JIN, Che-Ya CHOU, Wen-Sung HSU, Nan-Cheng CHEN
  • Publication number: 20170271265
    Abstract: An RDL structure on a passivation layer includes a first landing pad disposed directly above a first on-chip metal pad; a first via in a passivation layer to electrically connect the first landing pad with the first on-chip metal pad; a second landing pad disposed directly above the second on-chip metal pad; a second via in the passivation layer to electrically connect the second landing pad with the second on-chip metal pad; and at least five traces being disposed on the passivation layer and passing through a space between the first landing pad and the second landing pad.
    Type: Application
    Filed: June 3, 2017
    Publication date: September 21, 2017
    Inventors: Shih-Yi Syu, Tung-Hsien Hsieh, Che-Ya Chou
  • Patent number: 9704808
    Abstract: An RDL structure on a passivation layer includes a first landing pad disposed directly above a first on-chip metal pad; a first via in a passivation layer to electrically connect the first landing pad with the first on-chip metal pad; a second landing pad disposed directly above the second on-chip metal pad; a second via in the passivation layer to electrically connect the second landing pad with the second on-chip metal pad; and at least five traces being disposed on the passivation layer and passing through a space between the first landing pad and the second landing pad.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: July 11, 2017
    Assignee: MEDIATEK INC.
    Inventors: Shih-Yi Syu, Tung-Hsien Hsieh, Che-Ya Chou
  • Publication number: 20170053849
    Abstract: A die includes a semiconductor substrate, a through-via penetrating through the semiconductor substrate, a seal ring overlying and connected to the through-via, and an electrical connector underlying the semiconductor substrate and electrically coupled to the seal ring through the through-via.
    Type: Application
    Filed: November 7, 2016
    Publication date: February 23, 2017
    Inventors: Jing-Cheng Lin, Shih-Yi Syu
  • Patent number: 9490190
    Abstract: A die includes a semiconductor substrate, a through-via penetrating through the semiconductor substrate, a seal ring overlying and connected to the through-via, and an electrical connector underlying the semiconductor substrate and electrically coupled to the seal ring through the through-via.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: November 8, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Shih-Yi Syu
  • Publication number: 20160276277
    Abstract: An RDL structure on a passivation layer includes a first landing pad disposed directly above a first on-chip metal pad; a first via in a passivation layer to electrically connect the first landing pad with the first on-chip metal pad; a second landing pad disposed directly above the second on-chip metal pad; a second via in the passivation layer to electrically connect the second landing pad with the second on-chip metal pad; and at least five traces being disposed on the passivation layer and passing through a space between the first landing pad and the second landing pad.
    Type: Application
    Filed: January 25, 2016
    Publication date: September 22, 2016
    Inventors: Shih-Yi Syu, Tung-Hsien Hsieh, Che-Ya Chou
  • Patent number: 8816495
    Abstract: A device includes a package component, and a die over and bonded to the package component. The die includes a substrate. A heat sink is disposed over and bonded to a back surface of the substrate through direct bonding.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: August 26, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung Yu Wang, Shih-Yi Syu, Jing-Cheng Lin
  • Publication number: 20140084476
    Abstract: A die includes a semiconductor substrate, a through-via penetrating through the semiconductor substrate, a seal ring overlying and connected to the through-via, and an electrical connector underlying the semiconductor substrate and electrically coupled to the seal ring through the through-via.
    Type: Application
    Filed: September 21, 2012
    Publication date: March 27, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jing-Cheng Lin, Shih-Yi Syu
  • Patent number: 8629043
    Abstract: A method includes performing a dicing on a composite wafer including a plurality of dies, wherein the composite wafer is bonded on a carrier when the step of dicing is performed. After the step of dicing, the composite wafer is mounted onto a tape. The carrier is then de-bonded from the composite wafer and the first tape.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: January 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung Yu Wang, Jui-Pin Hung, Chih-Hao Chen, Chun-Hsing Su, Yi-Chao Mao, Kung-Chen Yeh, Yi-Lin Tsai, Ying-Tz Hung, Chin-Fu Kao, Shih-Yi Syu, Chin-Chuan Chang, Hsien-Wen Liu, Long Hua Lee
  • Publication number: 20130217188
    Abstract: A device includes a package component, and a die over and bonded to the package component. The die includes a substrate. A heat sink is disposed over and bonded to a back surface of the substrate through direct bonding.
    Type: Application
    Filed: February 16, 2012
    Publication date: August 22, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung Yu Wang, Shih-Yi Syu, Jing-Cheng Lin
  • Publication number: 20130122689
    Abstract: A method includes performing a dicing on a composite wafer including a plurality of dies, wherein the composite wafer is bonded on a carrier when the step of dicing is performed. After the step of dicing, the composite wafer is mounted onto a tape. The carrier is then de-bonded from the composite wafer and the first tape.
    Type: Application
    Filed: November 16, 2011
    Publication date: May 16, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung Yu Wang, Jui-Pin Hung, Chih-Hao Chen, Chun-Hsing Su, Yi-Chao Mao, Kung-Chen Yeh, Yi-Lin Tsai, Ying-Tz Hung, Chin-Fu Kao, Shih-Yi Syu, Chin-Chuan Chang, Hsien-Wen Liu, Long Hua Lee