Abstract: The method for performing a task on unified information units in a personal workspace, comprising: plugging at least one information importer and at least one unified tool to a personal workspace; obtaining at least one information via the at least one information importer from at least one of a plurality of information sources and unifying the at least one information into at least one unified information unit; arranging the at least one unified information unit and the at least one unified tool in the personal workspace; and performing the task for accessing or controlling the at least one unified information unit by using the at least one unified tool.

Abstract: The method for performing a task on unified information units in a personal workspace, comprising: plugging at least one information importer and at least one unified tool to a personal workspace; obtaining at least one information via the at least one information importer from at least one of a plurality of information sources and unifying the at least one information into at least one unified information unit; arranging the at least one unified information unit and the at least one unified tool in the personal workspace; and performing the task for accessing or controlling the at least one unified information unit by using the at least one unified tool.

Abstract: The present invention relates to a method of unifying information and tool from a plurality of information sources, comprising (i) providing an access scheme to retrieve attributes and associated link from an original information and/or tool, requested from the plurality of information sources; and (ii) modeling with one unified data model the original information into a unified information unit via re-organizing the attributes and associated link of the original information, and modeling with another unified data model the tool into a unified tool via re-organizing the attributes and associated link of the tool, wherein the one unified data model and/or the another unified data model respectively serves for modeling format of the original information and/or the tool.

Abstract: A transversal filter circuit comprises a plurality of delay units, a plurality of multiplexers and a plurality of full adders. The plurality of delay units is coupled in series to delay a two-bit input signal. The plurality of multiplexers is coupled to the plurality of delay units in a one-to-one manner, and outputs zero, a data signal, or the inverse of the data signal according to the output signals of the plurality of delay units. The plurality of full adders accumulates the outputs of the plurality of multiplexers and the MSB of the outputs of the plurality of the delay units.

Abstract: A power-saving method for Viterbi decoder and bit processing circuit of wireless receiver is provided. In response to various computational load of bit processing circuit and/or Viterbi decoder of a wireless receiver, the method is used for adjusting duty cycle of the bit processing circuit and/or the Viterbi decoder so as to save power in addition, in response to various data rates of the wireless receiver, the Viterbi decoder and the bit processing circuit are provided with power based on various duty cycles of related time pulse signals, thereby preventing the Viterbi decoder and/or the bit processing circuit from consuming power while being idle (during time segments of idle operation), so as to reduce power consumption.

Abstract: A method for writing a memory of a block interleaver determines in a bit-wise manner whether to write data into the memory. A method for reading a memory of a block interleaver combines two adjacent columns of the memory into a temporary column and reads data from the temporary column.

Abstract: A clock gating system includes a clock divider, a first clock gating unit and a second clock gating unit. The clock divider is employed to generate clock signals with different frequencies. The first clock gating unit is configured for generating a gated clock to a first functional block, while the second clock gating unit is configured for generating a gated clock to a second functional block. Logically the first clock gating unit and the second clock gating unit are included in the first functional block and the to second functional block, respectively, and in physical layout the first clock gating unit and the second clock gating unit are disposed close to the clock divider.

Abstract: A method for writing a memory of a block interleaver determines in a bit-wise manner whether to write data into the memory. A method for reading a memory of a block interleaver combines two adjacent columns of the memory into a temporary column and reads data from the temporary column.

Abstract: A transversal filter circuit comprises a plurality of delay units, a plurality of multiplexers and a plurality of full adders. The plurality of delay units is coupled in series to delay a two-bit input signal. The plurality of multiplexers is coupled to the plurality of delay units in a one-to-one manner, and outputs zero, a data signal, or the inverse of the data signal according to the output signals of the plurality of delay units. The plurality of full adders accumulates the outputs of the plurality of multiplexers and the MSB of the outputs of the plurality of the delay units.

Abstract: The frame of data is partitioned into a plurality of portions of data symbols. A plurality of channel elements is assigned to demodulate data symbols of correspondingly the plurality of portions of data symbols. The number of the plurality of portions of data symbols is higher in a case at high data rate than a case at low data rate.

Abstract: An apparatus for deinterleaving OFDM signals comprises a block deinterleaving memory, a computing module, a processed-tone buffer and a subcarrier rotator. The block deinterleaving memory is configured to store unprocessed symbols of the OFDM signals. The computing module is configured to access the block deinterleaving memory in accordance with the order of a first interleaving action for the OFDM signals and to compute thereafter. The processed-tone buffer is configured to store processed symbols of the OFDM signals. The subcarrier rotator is configured to access the processed-tone buffer and to perform a second interleaving action for the OFDM signals.

Abstract: A power-saving method for Viterbi decoder and bit processing circuit of wireless receiver is provided. In response to various computational load of bit processing circuit and/or Viterbi decoder of a wireless receiver, the method is used for adjusting duty cycle of the bit processing circuit and/or the Viterbi decoder so as to save power in addition, in response to various data rates of the wireless receiver, the Viterbi decoder and the bit processing circuit are provided with power based on various duty cycles of related time pulse signals, thereby preventing the Viterbi decoder and/or the bit processing circuit from consuming power while being idle (during time segments of idle operation), so as to reduce power consumption.

Abstract: The frame of data is partitioned into a plurality of portions of data symbols. A plurality of channel elements (300) is assigned to demodulate data symbols of correspondingly the plurality of portions of data symbols. The number of the plurality of portions of data symbols is higher in a case at high data rate than a case at low data rate.