Abstract: A pixel structure includes a patterned semiconductor layer disposed on a transistor region of the substrate, a first capacitor electrode disposed on a capacitor region of the substrate, a gate dielectric layer disposed on the first capacitor electrode, a gate disposed on a channel region of the patterned semiconductor layer, a second capacitor electrode, a dielectric layer, and an aluminum capacitor electrode sequentially disposed on the gate dielectric layer of the capacitor region, a first dielectric layer disposed on the gate and the aluminum capacitor electrode, at least one first wire disposed in the first dielectric layer for electrically connecting source/drain region of the patterned semiconductor layer and the aluminum capacitor electrode, a second dielectric layer disposed on the first wire, and a first transparent conductive layer disposed on the second dielectric layer and connected to the first wire.

Abstract: A pixel structure includes a patterned semiconductor layer disposed on a transistor region of the substrate, a first capacitor electrode disposed on a capacitor region of the substrate, a gate dielectric layer disposed on the first capacitor electrode, a gate disposed on a channel region of the patterned semiconductor layer, a second capacitor electrode, a dielectric layer, and an aluminum capacitor electrode sequentially disposed on the gate dielectric layer of the capacitor region, a first dielectric layer disposed on the gate and the aluminum capacitor electrode, at least one first wire disposed in the first dielectric layer for electrically connecting source/drain region of the patterned semiconductor layer and the aluminum capacitor electrode, a second dielectric layer disposed on the first wire, and a first transparent conductive layer disposed on the second dielectric layer and connected to the first wire.

Abstract: A method for fabricating pixel structures is disclosed. Specifically, the present invention deposits a conductive layer, a gate dielectric layer, and an aluminum layer on a gate dielectric layer, and performs an isotropic etching process to evenly etch a portion of the aluminum layer in the horizontal and vertical direction. By following this process, the number of photomasks used before the formation of the source/drain region can be reduced, and the conductive layer and the aluminum layer disposed on the capacitor electrode in the capacitor region can be used to increase the capacitance of the capacitor.

Abstract: A method for fabricating pixel structures is disclosed. Specifically, the present invention deposits a conductive layer, a gate dielectric layer, and an aluminum layer on a gate dielectric layer, and performs an isotropic etching process to evenly etch a portion of the aluminum layer in the horizontal and vertical direction. By following this process, the number of photomasks used before the formation of the source/drain region can be reduced, and the conductive layer and the aluminum layer disposed on the capacitor electrode in the capacitor region can be used to increase the capacitance of the capacitor.

Abstract: A method for fabricating metal oxide semiconductor with lightly doped drain. In the method, the gate electrode, the LDD of the n-type MOS TFT, and the source/drain electrode of the p-type MOS TFT are defined simultaneously in one photolithography step. The contact holes and the source/drain electrode of the n-type MOS TFT are also defined simultaneously in one photolithography step. The invention employs only six photolithography steps to manufacture the metal oxide semiconductor, such as TFT, with lightly doped drain, thereby avoiding alignment errors, further improving yield and increasing throughput.

Abstract: A method for fabricating metal oxide semiconductor with lightly doped drain. In the method, the gate electrode, the LDD of the n-type MOS TFT, and the source/drain electrode of the p-type MOS TFT are defined simultaneously in one photolithography step. The contact holes and the source/drain electrode of the n-type MOS TFT are also defined simultaneously in one photolithography step. The invention employs only six photolithography steps to manufacture the metal oxide semiconductor, such as TFT, with lightly doped drain, thereby avoiding alignment errors, further improving yield and increasing throughput.

Abstract: A mask for fabricating contacts is provided. The mask has a contact pattern with an edge pattern around the edge of the contact pattern. The edge pattern is a half-tone region. Due to the half-tone edge pattern on the mask, contact angle between the sidewall of the contact opening and an underlying conductive layer after a patterning process is reduced.