Patents by Inventor Shih-Ying Liu
Shih-Ying Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11973021Abstract: A semiconductor device includes a first metal layer, a second metal layer, and an inter-metal dielectric layer disposed between the first metal layer and the second metal layer. The inter-metal dielectric layer includes: a first dielectric layer disposed on the first metal layer and in direct contact with the first metal layer, wherein the first dielectric layer has a stress value less than 0; a second dielectric layer disposed on the first dielectric layer, wherein the second dielectric layer has a stress value greater than 0; and a third dielectric layer disposed on the second dielectric layer, wherein the third dielectric layer has a stress value less than 0. A thickness of the third dielectric layer is greater than a thickness of the second dielectric layer, and the thickness of the second dielectric layer is greater than a thickness of the first dielectric layer.Type: GrantFiled: September 17, 2021Date of Patent: April 30, 2024Assignee: Vanguard International Semiconductor CorporationInventors: Kai-Chun Chen, Shih-Ming Tseng, Hsing-Chao Liu, Hsiao-Ying Yang
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Patent number: 11727178Abstract: A method includes generating a channel configuration between a first signal pin of a first integrated circuit (IC) die and a second signal pin of a second IC die based on a multiplex data rate (XDR) of the first signal pin and the second signal pin. The channel configuration includes an association of the XDR to a channel. The method also includes determining a signal pin channel assignment based on the channel configuration, updating the channel configuration based on the signal pin channel assignment and a wirelength representative of a total distance between the first signal pin, the second signal pin, and physical ports of the channel, and performing socket instantiation based on the updated channel configuration and the signal pin channel assignment.Type: GrantFiled: September 29, 2021Date of Patent: August 15, 2023Assignee: Synopsys, Inc.Inventors: Yu Yang, Jianfeng Huang, Shih-Ying Liu
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Publication number: 20220100942Abstract: A method includes generating a channel configuration between a first signal pin of a first integrated circuit (IC) die and a second signal pin of a second IC die based on a multiplex data rate (XDR) of the first signal pin and the second signal pin. The channel configuration includes an association of the XDR to a channel. The method also includes determining a signal pin channel assignment based on the channel configuration, updating the channel configuration based on the signal pin channel assignment and a wirelength representative of a total distance between the first signal pin, the second signal pin, and physical ports of the channel, and performing socket instantiation based on the updated channel configuration and the signal pin channel assignment.Type: ApplicationFiled: September 29, 2021Publication date: March 31, 2022Inventors: Yu YANG, Jianfeng HUANG, Shih-Ying LIU
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Patent number: 10162927Abstract: A method for redistributing cell densities in layout of IC is provided. Initial cell density distribution and routing density distribution are obtained in an initial placement of the IC. White space is inserted into the initial placement according to a specific density value, so as to flatten the initial cell density distribution to the specific density value and obtain a flat cell density distribution. The specific density value is larger than a maximum cell density value within the initial cell density distribution. Cell densities of a first region are increased in the IC according to the routing density distribution and the flat cell density distribution, so as to obtain a modified cell density distribution. The modified cell density distribution is smoothed to obtain a calibrated cell density distribution. The white space is removed from the calibrated cell density distribution to obtain a final placement.Type: GrantFiled: March 8, 2018Date of Patent: December 25, 2018Assignee: MEDIATEK INC.Inventors: Shih-Ying Liu, Chin-Hsiung Hsu, Chi-Yuan Liu, Chun-Chih Yang, Chao-Neng Huang
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Publication number: 20180196910Abstract: A method for redistributing cell densities in layout of IC is provided. Initial cell density distribution and routing density distribution are obtained in an initial placement of the IC. White space is inserted into the initial placement according to a specific density value, so as to flatten the initial cell density distribution to the specific density value and obtain a flat cell density distribution. The specific density value is larger than a maximum cell density value within the initial cell density distribution. Cell densities of a first region are increased in the IC according to the routing density distribution and the flat cell density distribution, so as to obtain a modified cell density distribution. The modified cell density distribution is smoothed to obtain a calibrated cell density distribution. The white space is removed from the calibrated cell density distribution to obtain a final placement.Type: ApplicationFiled: March 8, 2018Publication date: July 12, 2018Inventors: Shih-Ying LIU, Chin-Hsiung HSU, Chi-Yuan LIU, Chun-Chih YANG, Chao-Neng HUANG
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Patent number: 9946829Abstract: A method for redistributing cell densities in layout of IC is provided. Initial cell density distribution and routing density distribution are obtained in an initial placement of the IC. White space is inserted into the initial placement according to a specific density value, so as to flatten the initial cell density distribution to the specific density value and obtain a flat cell density distribution. The specific density value is larger than a maximum cell density value within the initial cell density distribution. Cell densities of a first region are increased in the IC according to the routing density distribution and the flat cell density distribution, so as to obtain a modified cell density distribution. The modified cell density distribution is smoothed to obtain a calibrated cell density distribution. The white space is removed from the calibrated cell density distribution to obtain a final placement.Type: GrantFiled: November 4, 2015Date of Patent: April 17, 2018Assignee: MEDIATEK INC.Inventors: Shih-Ying Liu, Chin-Hsiung Hsu, Chi-Yuan Liu, Chun-Chih Yang, Chao-Neng Huang
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Patent number: 9892226Abstract: A method for providing a macro placement of an integrated circuit is provided. An initial placement of the integrated circuit is obtained, wherein the initial placement includes a plurality of first macro blocks. The first macro blocks are divided into a plurality of groups according to the hierarchy of the integrated circuit. A value of layout area is obtained for each of the groups according to macro areas of the first macro blocks. A plurality of candidate placements are obtained for each of the groups according to the value of placement area corresponding to the group, wherein the candidate placement includes the first macro blocks corresponding to the group. A first macro placement is obtained according to a specific placement o selecting from the candidate placements for each of the groups.Type: GrantFiled: May 5, 2016Date of Patent: February 13, 2018Assignee: MEDIATEK INC.Inventors: Chin-Hsiung Hsu, Chun-Chih Yang, Shih-Ying Liu, Che-Jung Lou, Chao-Neng Huang, Chi-Yuan Liu
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Publication number: 20160335386Abstract: A method for providing a macro placement of an integrated circuit is provided. An initial placement of the integrated circuit is obtained, wherein the initial placement includes a plurality of first macro blocks. The first macro blocks are divided into a plurality of groups according to the hierarchy of the integrated circuit. A value of layout area is obtained for each of the groups according to macro areas of the first macro blocks. A plurality of candidate placements are obtained for each of the groups according to the value of placement area corresponding to the group, wherein the candidate placement includes the first macro blocks corresponding to the group. A first macro placement is obtained according to a specific placement o selecting from the candidate placements for each of the groups.Type: ApplicationFiled: May 5, 2016Publication date: November 17, 2016Inventors: Chin-Hsiung HSU, Chun-Chih YANG, Shih-Ying LIU, Che-Jung LOU, Chao-Neng HUANG, Chi-Yuan LIU
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Publication number: 20160232272Abstract: A method for redistributing cell densities in layout of IC is provided. Initial cell density distribution and routing density distribution are obtained in an initial placement of the IC. White space is inserted into the initial placement according to a specific density value, so as to flatten the initial cell density distribution to the specific density value and obtain a flat cell density distribution. The specific density value is larger than a maximum cell density value within the initial cell density distribution. Cell densities of a first region are increased in the IC according to the routing density distribution and the flat cell density distribution, so as to obtain a modified cell density distribution. The modified cell density distribution is smoothed to obtain a calibrated cell density distribution. The white space is removed from the calibrated cell density distribution to obtain a final placement.Type: ApplicationFiled: November 4, 2015Publication date: August 11, 2016Inventors: Shih-Ying LIU, Chin-Hsiung HSU, Chi-Yuan LIU, Chun-Chih YANG, Chao-Neng HUANG
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Patent number: 5211460Abstract: A shoe closet comprises a compartment for the storage and retrieval of shoes, a number of shoe-plate modules on which shoes are placed, a conveyor assembly for carrying shoes to a desired position, and a driving unit for driving the conveyor assembly. The conveyor assembly includes a first conveyor device disposed at an inner edge of the compartment for an upward movement of the shoe-plate module and a second conveyor device disposed at an outer edge of the compartment for a downward movement of the shoe-plate module.Type: GrantFiled: July 29, 1991Date of Patent: May 18, 1993Inventor: Shih-Ying Liu