Abstract: A cyclic process including an etching process, a passivation process, and a pumping out process is provided to prevent over etching of the sacrificial gate electrode, particularly when near a high-k dielectric feature. The cyclic process solves the problems of failed gate electrode layer at an end of channel region and enlarges filling windows for replacement gate structures, thus improving channel control. Compared to state-of-art solutions, embodiments of the present disclosure also enlarge volume of source/drain regions, thus improving device performance.

Abstract: A semiconductor structure includes an epitaxial region having a front side and a backside. The semiconductor structure includes an amorphous layer formed over the backside of the epitaxial region, wherein the amorphous layer includes silicon. The semiconductor structure includes a first silicide layer formed over the amorphous layer. The semiconductor structure includes a first metal contact formed over the first silicide layer.

Abstract: A method for forming a semiconductor device includes patterning a substrate to form a strip including a first semiconductor material, forming an isolation region along a sidewall of the strip, an upper portion of the strip extending above the isolation region, forming a dummy structure along sidewalls and a top surface of the upper portion of the strip, performing a first etching process on an exposed portion of the upper portion of the strip to form a first recess, the exposed portion of the strip being exposed by the dummy structure, after performing the first etching process, reshaping the first recess to have a V-shaped bottom surface using a second etching process, wherein the second etching process is selective to first crystalline planes having a first orientation relative to second crystalline planes having a second orientation, and epitaxially growing a source/drain region in the reshaped first recess.

Abstract: A method of forming a semiconductor device structure is disclosed. First and second etch stop layers are formed overlying a semiconductor structure having a conductive feature formed therein. A dielectric layer is formed overlying the second etch stop layer, and a hard mask, that comprises a tungsten-based material, is formed overlying the dielectric layer, and patterned. A resist layer is formed over the patterned hard mask. Using the patterned resist layer as a mask, a first etching process is performed to form a via opening that extends partially through the dielectric layer. Using the patterned hard mask as an etch mask, a second etching process (e.g., dry etching process) is performed to extend the via opening through the second etch stop layer, and a third etching process (e.g., wet etching process) is performed to extend the via opening through the first etch stop layer to reach the conductive feature.

Abstract: A method includes removing a dummy gate to form a gate trench. A gate dielectric layer is deposited over a bottom and sidewalls of the gate trench. A first work function metal layer is deposited over the gate dielectric layer. A dummy layer is deposited over the first work function metal layer. An impurity is introduced into the dummy layer and the first work function metal layer after the dummy layer is deposited. The dummy layer is removed after the impurity is introduced into the dummy layer and the first work function metal layer. The gate trench is filled with a conductive material after the dummy layer is removed.

Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

Abstract: Disclosed are methods and the non-transitory computer storage media of extracting linguistic patterns and summarizing a pathology report thereof. The present disclosure provides a method of extracting key linguistic patterns from a pathology report. The method comprises: determining a confidence degree and a support degree between a linguistic term and a next linguistic term based on co-occurrences of the linguistic term and the next linguistic term; generating a set of candidate linguistic terms; generating a first set of linguistic patterns through performing random walks on the set of candidate linguistic terms; and determining the key linguistic patterns through removing redundant linguistic patterns from the first set of linguistic patterns.

Abstract: A semiconductor device includes a fin protruding from a substrate and extending in a first direction, a gate structure extending on the fin in a second direction, and a seal layer located on the sidewall of the gate structure. A first peak carbon concentration is disposed in the seal layer. A first spacer layer is located on the seal layer. A second peak carbon concentration is disposed in the first spacer layer. A second spacer layer is located on the first spacer layer.

Abstract: A storage device of the present invention is provided to store flexible circuit packages, each of the flexible circuit packages includes an electronic component and two circuit portions warped at both sides of the electronic component, respectively. The storage device includes a first carrier and a second carrier. The first carrier includes first accommodation elements provided for placement of the flexible circuit packages, and the second carrier includes a first press portion and a second press portion. As the second carrier is placed on the first carrier, the first and second press portions are provided to press the two circuit portions warped upwardly toward the second carrier so as to reduce the warpage of the two circuit portions.

Abstract: The image sensor includes a semiconductor substrate, a pillar array layer, a planar layer, and a microlens layer. The semiconductor substrate includes a first photodiode and a second photodiode. The pillar array layer is disposed on the semiconductor substrate, the pillar array layer includes a first pillar array disposed above the first photodiode and a second pillar array disposed above the second photodiode. The first pillar array includes a plurality of first pillar structures, the second pillar array includes a plurality of second pillar structures, all the first pillar structures have a first height, and all the second pillar structures have a second height. The planar layer is disposed on the pillar array layer. The microlens layer is disposed on the planar layer.

Abstract: A semiconductor structure includes an epitaxial region having a front side and a backside. The semiconductor structure includes an amorphous layer formed over the backside of the epitaxial region, wherein the amorphous layer includes silicon. The semiconductor structure includes a first silicide layer formed over the amorphous layer. The semiconductor structure includes a first metal contact formed over the first silicide layer.

Abstract: A method includes providing a substrate having a gate structure over a first side of the substrate, forming a recess adjacent to the gate structure, and forming in the recess a first semiconductor layer having a dopant, the first semiconductor layer being non-conformal, the first semiconductor layer lining the recess and extending from a bottom of the recess to a top of the recess. The method further includes forming a second semiconductor layer having the dopant in the recess and over the first semiconductor layer, a second concentration of the dopant in the second semiconductor layer being higher than a first concentration of the dopant in the first semiconductor layer.

Abstract: A device includes a fin protruding from a semiconductor substrate; a gate stack over and along a sidewall of the fin; a gate spacer along a sidewall of the gate stack and along the sidewall of the fin; an epitaxial source/drain region in the fin and adjacent the gate spacer; and a corner spacer between the gate stack and the gate spacer, wherein the corner spacer extends along the sidewall of the fin, wherein a first region between the gate stack and the sidewall of the fin is free of the corner spacer, wherein a second region between the gate stack and the gate spacer is free of the corner spacer.

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a device substrate, a resistance variable layer and a top electrode. The bottom electrode is disposed on the device substrate. The resistance variable layer is disposed on the bottom electrode. The top electrode is disposed on the resistance variable layer. The bottom electrode is formed with a tensile stress, while the top electrode is formed with a compressive stress.

Abstract: Provided is a multi-axis force sensing device, including a central portion, an outer ring portion, multiple measurement shafts, and multiple sensing groups. The outer ring portion surrounds the central portion. The measurement shafts are respectively connected between the central portion and the outer ring portion. The measurement shafts are equally disposed on an outer side of the central portion. A first surface and a second surface of each measurement shaft are respectively disposed with one of the sensing groups. Each sensing group includes a first strain sensing element and a second strain sensing element. The first strain sensing element is disposed on a first central line of symmetry on the first surface or on a second central line of symmetry on the second surface. The second strain sensing element is disposed on the first surface or the second surface.

Abstract: A method includes forming a conductive member over a first conductive line; forming a second conductive line over the conductive member; and removing a portion of the conductive member exposed by the second conductive line to form a conductive via. The formation of the second conductive line is implemented prior to the formation of the conductive via. A semiconductor structure includes a first conductive line having a first surface; a second conductive line disposed above the first conductive line and having a second surface overlapping the first surface; and a conductive via electrically connected to the first surface and the second surface. The conductive via includes a first end disposed within the first surface, a second end disposed within the second surface, and a cross-section between the first end and the second end, wherein at least two of interior angles of the cross-section are substantially unequal to 90°.

Abstract: A dopant boost in the source/drain regions of a semiconductor device, such as a transistor can be provided. A semiconductor device can include a doped epitaxy of a first material having a plurality of boosting layers embedded within. The boosting layers can be of a second material different from the first material. Another device can include a source/drain feature of a transistor. The source/drain feature includes a doped source/drain material and one or more embedded distinct boosting layers. A method includes growing a boosting layer in a recess of a substrate, where the boosting layer is substantially free of dopant. The method also includes growing a layer of doped epitaxy in the recess on the boosting layer.

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a device substrate, a resistance variable layer and a top electrode. The bottom electrode is disposed on the device substrate. The resistance variable layer is disposed on the bottom electrode. The top electrode is disposed on the resistance variable layer. The bottom electrode is formed with a tensile stress, while the top electrode is formed with a compressive stress.

Abstract: A rotary engine is provided, including: a stator assembly, including an intake stator including an annular intake groove and an exhaust stator including an annular exhaust groove which define a track therebetween; a rotor, rotatably disposed between the intake and exhaust stators, including cylinders each being covered by one of the cylinder head and cylinder heads each including an intake port and an exhaust port, the intake and exhaust ports being connected to the annular intake and exhaust grooves, respectively; a shaft, inserted axially in the stator assembly and the rotor; valve mechanisms, posited on the cylinder heads respectively and each including an intake valve and an exhaust valve; pistons, received in the cylinders respectively and each including a piston rod which is movable along the track; and spark plugs, posited on the cylinder heads and exposed to interiors of the cylinders, respectively.

Abstract: A joint actuator of a robot includes a casing, a driving device, a driving shaft, a reducer, and a sensor. The driving device is disposed in the casing. The driving shaft is disposed in the casing and connected to the driving device, and the driving device is adapted to drive the driving shaft to rotate. The reducer is disposed in the casing and includes a power input component and a power output component. The power input component and the power output component are sleeved around the driving shaft, and the power input component is connected between the driving shaft and the power output component. The sensor is disposed on the power input component or the casing.