Patents by Inventor Shih-Yu Huang

Shih-Yu Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240118526
    Abstract: An imaging system lens assembly includes a first lens group and a second lens group. The first lens group includes a first catadioptric lens element and a second catadioptric lens element, the second lens group includes at least one lens element. Each of an object-side surface and an image-side surface of the first catadioptric lens element and the second catadioptric lens element includes a central region and a peripheral region. The peripheral region of the object-side surface of the first catadioptric lens element includes a first refracting surface. The peripheral region of the image-side surface of the second catadioptric lens element includes a first reflecting surface. The central region of the object-side surface of the first catadioptric lens element includes a second reflecting surface. The central region of the image-side surface of the second catadioptric lens element includes a last refracting surface.
    Type: Application
    Filed: September 26, 2023
    Publication date: April 11, 2024
    Inventors: Shih-Han CHEN, Cheng-Yu TSAI, Hsin-Hsuan HUANG
  • Patent number: 11946569
    Abstract: An actuating and sensing module is disclosed and includes a bottom plate, a gas pressure sensor, a thin gas transportation device and a cover plate. The bottom plate includes a pressure relief orifice, a discharging orifice and a communication orifice. The gas pressure sensor is disposed on the bottom plate and seals the communication orifice. The thin gas transportation device is disposed on the bottom plate and seals the pressure relief orifice and the discharging orifice. The cover plate is disposed on the bottom plate and covers the gas pressure sensor and the thin gas-transportation device. The cover plate includes an intake orifice. The thin gas transportation device is driven to inhale gas through the intake orifice, the gas is then discharged through the discharging orifice by the thin gas transportation device, and a pressure change of the gas is sensed by the gas pressure sensor.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: April 2, 2024
    Assignee: MICROJET TECHNOLOGY CO., LTD.
    Inventors: Hao-Jan Mou, Shih-Chang Chen, Jia-Yu Liao, Hung-Hsin Liao, Chung-Wei Kao, Chi-Feng Huang, Yung-Lung Han, Chang-Yen Tsai, Wei-Ming Lee
  • Publication number: 20240096705
    Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Yu Kao, Chen-Yui Yang, Hsien-Chung Huang, Chao-Cheng Chen, Shih-Yao Lin, Chih-Chung Chiu, Chih-Han Lin, Chen-Ping Chen, Ke-Chia Tseng, Ming-Ching Chang
  • Patent number: 11935955
    Abstract: A device includes a fin extending from a substrate, a gate stack over and along sidewalls of the fin, a gate spacer along a sidewall of the gate stack, and an epitaxial source/drain region in the fin and adjacent the gate spacer. The epitaxial source/drain region includes a first epitaxial layer on the fin, the first epitaxial layer including silicon, germanium, and arsenic, and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including silicon and phosphorus, the first epitaxial layer separating the second epitaxial layer from the fin. The epitaxial source/drain region further includes a third epitaxial layer on the second epitaxial layer, the third epitaxial layer including silicon, germanium, and phosphorus.
    Type: Grant
    Filed: December 2, 2022
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yu Ma, Shahaji B. More, Yi-Min Huang, Shih-Chieh Chang
  • Patent number: 11934027
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: March 19, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Publication number: 20240087207
    Abstract: Disclosed herein are system, method, and computer program product embodiments for reducing GPU load by programmatically controlling shading rates in computer graphics. GPU load may be reduced by applying different shading rates to different screen regions. By reading the depth buffer of previous frames and performing image processing, thresholds may be calculated that control the shading rates. The approach may be run on any platform that supports VRS hardware and primitive- or image-based VRS. The approach may be applied on a graphics driver installed on a client device, in a firmware layer between hardware and a driver, in a software layer between a driver and an application, or in hardware on the client device. The approach is flexible and adaptable and calculates and sets the variable rate shading based on the graphics generated by an application without requiring the application developer to manually set variable rate shading.
    Type: Application
    Filed: September 14, 2022
    Publication date: March 14, 2024
    Applicant: MediaTek Inc.
    Inventors: Po-Yu HUANG, Shih-Chin LIN, Jen-Jung CHENG, Tu-Hsiu LEE
  • Publication number: 20240083828
    Abstract: The present application relates to a system and a method for producing vinyl chloride. The system comprise a preheat unit, a gas-liquid separating unit, a heat-recovery unit, a heating unit and a thermal pyrolysis unit, and therefore heat energy of the thermal pyrolysis product can be efficiently recovered. Energy cost of the system can be efficiently lowered with the heat-recovery unit and the heating unit, and further prolonging operating cycle of the system.
    Type: Application
    Filed: June 28, 2023
    Publication date: March 14, 2024
    Inventors: Wen-Hsi HUANG, Sheng-Yen KO, Shih-Hong CHEN, Chun-Yu LIN
  • Patent number: 11923429
    Abstract: A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chang Cheng, Fu-Yu Chu, Ming-Ta Lei, Ruey-Hsin Liu, Shih-Fen Huang
  • Publication number: 20230402587
    Abstract: A battery material is a core-shell structure, and the core-shell structure includes a core and a shell. The shell surrounds the core. A composition of the core is a silicon material. The shell includes a polymer, the polymer is linear, the polymer includes a first structure and a second structure, the first structure includes a siloxane group, and the second structure includes a carboxyl group or an ester group. The first structure is more adjacent to the core than the second structure.
    Type: Application
    Filed: June 5, 2023
    Publication date: December 14, 2023
    Inventors: Wei-Yuan CHEN, Po-Tsun CHEN, Tzu Lien WANG, Shih Yu HUANG, Cheng-Yu TSAI, Chun-Hung TENG
  • Publication number: 20210060918
    Abstract: A method for manufacturing a composite material is provided, including following steps of: (1) providing a thermoplastic prepreg which includes a first fibrous layer pre-impregnated with thermoplastic resin, wherein the first fibrous layer includes at least one layer which has a thickness smaller than or equal to 0.1 min, and at least a portion of the at least one layer includes fibers of parallel; (2) providing a thermosetting prepreg which includes a second fibrous layer pre-impregnated with unsolidified thermosetting resin; (3) combining the thermoplastic prepreg with the thermosetting prepreg by thermoforming to form a non-smooth bonding interface therebetween; (4) cooling the thermoplastic prepreg and the thermosetting prepreg which are combined in the step (3) to form the composite material.
    Type: Application
    Filed: August 28, 2019
    Publication date: March 4, 2021
    Inventors: SHAO-CHEN CHIU, CHANG-TING LO, SHIH-YU HUANG
  • Patent number: 10831666
    Abstract: Techniques related to failover to the secondary storage server from a primary storage server of a database server without degrading the performance of servicing storage requests for client applications are provided. In an embodiment, the secondary storage server receives, from the database server, an eviction notification indicating that a set of data blocks has been evicted from a cache. The secondary storage server's memory hierarchy includes a secondary cache and a secondary persistent storage that stores a second copy of the set of data blocks. The secondary storage server persistently stores a copy of data, which is also persistently stored on the primary storage server, which includes a first copy of the set of data blocks.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: November 10, 2020
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Jia Shi, Wei Zhang, Vijayakrishnan Nagarajan, Shih-Yu Huang, Kothanda Umamageswaran
  • Patent number: 10797004
    Abstract: A semiconductor device package includes: (1) a lead frame including a connection element and multiple leads; (2) a package body encapsulating the lead frame, wherein the package body includes a lower surface and an upper surface opposite to the lower surface, the package body includes a cavity exposing at least one of the leads; (3) at least one conductive via disposed in the cavity of the package body, electrically connected to the connection element, and exposed from the upper surface of the package body; and (4) a conductive layer disposed on the upper surface of the package body and the conductive via.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: October 6, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shao-Lun Yang, Yu-Shun Hsieh, Chia Yi Cheng, Hong Jie Chen, Shih Yu Huang
  • Publication number: 20200110700
    Abstract: Techniques related to failover to the secondary storage server from a primary storage server of a database server without degrading the performance of servicing storage requests for client applications are provided. In an embodiment, the secondary storage server receives, from the database server, an eviction notification indicating that a set of data blocks has been evicted from a cache. The secondary storage server's memory hierarchy includes a secondary cache and a secondary persistent storage that stores a second copy of the set of data blocks. The secondary storage server persistently stores a copy of data, which is also persistently stored on the primary storage server, which includes a first copy of the set of data blocks.
    Type: Application
    Filed: October 5, 2018
    Publication date: April 9, 2020
    Inventors: JIA SHI, WEI ZHANG, VIJAYAKRISHNAN NAGARAJAN, SHIH-YU HUANG, KOTHANDA UMAMAGESWARAN
  • Publication number: 20190279941
    Abstract: A semiconductor device package includes: (1) a lead frame including a connection element and multiple leads; (2) a package body encapsulating the lead frame, wherein the package body includes a lower surface and an upper surface opposite to the lower surface, the package body includes a cavity exposing at least one of the leads; (3) at least one conductive via disposed in the cavity of the package body, electrically connected to the connection element, and exposed from the upper surface of the package body; and (4) a conductive layer disposed on the upper surface of the package body and the conductive via.
    Type: Application
    Filed: May 23, 2019
    Publication date: September 12, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Shao-Lun YANG, Yu-Shun HSIEH, Chia Yi CHENG, Hong Jie CHEN, Shih Yu HUANG
  • Publication number: 20190277251
    Abstract: The present invention a rotatory aerogenerator, which comprises: an axial rod; at least one first windward blade; at least one blade assembly; wherein each blade assembly component comprises: a first rod piece, a second windward blade and a second rod piece; wherein the first windward blade is pivotally connected with the first rod piece and the second rod piece for the flapping and folding activities of the second windward blade; and a supporting frame which top end is axially connected with the axial rod, so that the axial rod can rotate horizontally in the supporting frame. The rotatory aerogenerator of the present invention operates more efficiently and its upright design can be conveniently used in serial or in parallel and the user can use it in parallel by utilizing the same axial rod to achieve the effects of saving space and saving cost.
    Type: Application
    Filed: March 7, 2018
    Publication date: September 12, 2019
    Inventor: Shih-Yu Huang
  • Patent number: 10312198
    Abstract: A semiconductor device package includes a lead frame, an electronic component, a package body, at least one conductive via and a conductive layer. The lead frame includes a paddle, a connection element and a plurality of leads. The electronic component is disposed on the paddle. The package body encapsulates the electronic component and the lead frame. The at least one conductive via is disposed in the package body, electrically connected to the connection element, and exposed from the package body. The conductive layer is disposed on the package body and the conductive via.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: June 4, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shao-Lun Yang, Yu-Shun Hsieh, Chia Yi Cheng, Hong Jie Chen, Shih Yu Huang
  • Publication number: 20190122992
    Abstract: A semiconductor device package includes a lead frame, an electronic component, a package body, at least one conductive via and a conductive layer. The lead frame includes a paddle, a connection element and a plurality of leads. The electronic component is disposed on the paddle. The package body encapsulates the electronic component and the lead frame. The at least one conductive via is disposed in the package body, electrically connected to the connection element, and exposed from the package body. The conductive layer is disposed on the package body and the conductive via.
    Type: Application
    Filed: October 20, 2017
    Publication date: April 25, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Shao-Lun YANG, Yu-Shun HSIEH, Chia Yi CHENG, Hong Jie CHEN, Shih Yu HUANG
  • Publication number: 20180180021
    Abstract: The wind harnessing device includes an axle, a number of radially outward extending first and second poles respectively arranged at equal intervals around a first end and a second end of the axle, a number of blade assemblies, and a rack to which the axle is rotatably mounted. Each first pole is aligned with and parallel to a second pole. Each blade assembly includes a first beam, a second beam, and a flat blade. The first and second beams are respectively attached to and along a first edge and an opposite second edge of the blade. The first beam's two ends are pin joined to the outer ends of a pair of corresponding first and second poles so that the blade is able to swing about the first beam. The wind harnessing device thus structured is of lower weight, reduced cost, and easy maintenance.
    Type: Application
    Filed: October 23, 2017
    Publication date: June 28, 2018
    Inventor: SHIH-YU HUANG
  • Publication number: 20100212735
    Abstract: This invention discloses a high-efficiency solar cell structure which enables high throughput manufacturing process thereof. The solar cell is accomplished by forming a plurality of first emitter regions in a front surface of a substrate, a plurality of second emitter regions in the front surface, and a plurality of fingers. Each of the fingers is formed over a least a portion of the second emitter region and a portion of the first emitter region. The first emitter regions and the second emitter regions have a depth not less than 0.2 ?m.
    Type: Application
    Filed: January 6, 2010
    Publication date: August 26, 2010
    Inventors: Pin-Sheng Wang, Yi-Chin Chou, Shih-Cheng Lin, Shih-Yu Huang, Chia-Chen Tu
  • Publication number: 20060236204
    Abstract: The present invention provides a memory device with the serial transmission interface and an error correction method for the serial transmission interface. The memory device comprises an error correction mechanism to detect or automatically correct the error earlier to make sure the correctness of the data transmission while the serial transmission interface accesses the memory. Further, the action of error corrections and data re-transmissions performed by the master device can be reduced.
    Type: Application
    Filed: August 24, 2005
    Publication date: October 19, 2006
    Inventors: Yu-Chu Lee, Shih-Yu Huang, Han-Liang Chou