Abstract: A method comprises: providing a substrate comprising a first trench; forming an etch stop layer on the substrate; forming a silicon sacrificial region in the first trench; forming a first micromechanical arm array in the silicon sacrificial region; forming a second micromechanical arm array in the silicon sacrificial region; patterning and etching a top portion of each micromechanical arm in the first micromechanical arm array to form a protrusion; forming at least one polysilicon sacrificial layer on the micromechanical arms in the second micromechanical arm array and the micromechanical arms in the second micromechanical arm array, wherein the protrusion of each micromechanical arm in the first micromechanical arm array remains exposed; forming a metal layer; and removing the silicon sacrificial region and the at least one polysilicon sacrificial layer to create a cavity.

Abstract: A photonic device structure and method of fabricating the same. The structure includes a substrate that has a first top oxide layer and a silicon layer that is formed on the first top oxide layer. The structure further includes a plurality of rib waveguide components that are formed in the silicon layer. A first rib waveguide component of the plurality includes first contact holes having a first contact hole depth, and a second rib waveguide component of the plurality includes second contact holes having a second contact hole depth, such that the depths of the first contact hole and the second contact hole are different.

Abstract: A photonic device structure and method of fabricating the same. The structure includes a substrate that has a topside oxide layer and a silicon layer that is formed on the topside oxide layer. The structure further includes a rib waveguide component formed in the silicon layer and that includes contact holes. The contact holes include a contact hole depth, and a contact hole trench that is formed in the silicon layer and which has a first sidewall, a second sidewall, and a bottom surface. The contact hole further includes a contact etch stop layer formed in the contact hole trench.

Abstract: A photonic device, structure, and fabrication method that includes a substrate having a topside oxide layer formed thereon. The structure also includes a silicon layer that is formed on the topside oxide layer, and one or more waveguide components that are formed in the silicon layer. In addition, the structure includes a reflection device trench structure that is formed in the silicon layer, and which includes a first oblique plane, a bottom plane, and a second oblique plane. The photonic structure also includes a reflection device that is formed adjacent to the first oblique plane, and which has a reflection device angle relative to the bottom plane and configured to direct light into a waveguide component.

Abstract: A deep trench resistor structure and methods of forming the same are described. The structure includes a first trench located in a first dielectric material, a first layer disposed over the first dielectric material, a second layer disposed on the first layer, a second dielectric material disposed over the second layer, and a tunable device in contact with the first layer. The tunable device includes a semiconductor-containing layer in contact with the first layer, a dielectric layer disposed on the semiconductor-containing layer, and a metal-containing layer disposed on the dielectric layer.

Abstract: The present disclosure describes a resistor structure with a dielectric layer, trenches, a metal layer, a semiconductor layer, and an insulating layer. The dielectric layer is disposed above electrical components formed on a substrate. The trenches are disposed in the dielectric layer and separated from each other by a dielectric region of the dielectric layer. The metal layer is disposed on a bottom surface and side surfaces of each of the trenches and on a top surface of the dielectric region. The semiconductor layer is disposed on a bottom surface, side surfaces, and a top surface of the metal layer. The insulating layer is disposed in the trenches and in contact with side surfaces of the semiconductor layer and on a top surface of the semiconductor layer.

Abstract: Various embodiments of the present disclosure are directed to a vertical gate-all-around (GAA) memory cell. A middle conductor overlies a lower conductor and decreases in width towards the lower conductor to culminate in a point spaced from the lower conductor. An insulator structure is between the lower conductor and the middle conductor. A semiconductor channel overlies the middle conductor, and a gate electrode laterally surrounds the semiconductor channel on a sidewall of the semiconductor channel. A gate dielectric layer separates the gate electrode from the semiconductor channel, and an upper conductor overlies the semiconductor channel. The lower and middle conductors and the insulator structure correspond to a resistor, whereas the middle conductor, the upper conductor, the gate electrode, the gate dielectric layer, and the semiconductor channel correspond to a transistor atop the resistor.

Abstract: A semiconductor device with an image sensor and a method of fabricating the same are disclosed. The semiconductor device includes a substrate, a pixel region with a pixel structure, an isolation region with an isolation structure disposed adjacent to the pixel region, and a contact pad region with a pad structure disposed adjacent to the isolation region. The pixel structure includes an epitaxial structure, which includes an embedded portion with a stepped structure disposed in the substrate and a protruding portion extending above a top surface of the substrate. The pixel structure further includes a capping layer disposed on the protruding portion.

Abstract: Some implementations described herein provide an optoelectronic device including a multi-layer photodiode structure having multiple sensing structures formed from one or more quantum effect materials (e.g., formed from multiple layers of quantum effect materials). The multiple sensing structures, which include sidewalls that are in contact with a substrate of the optoelectronic device, may be stacked and include overlapping portions. Through use of the multi-layer photodiode structure including the multiple sensing structures, a quantum length is increased relative to another photodiode structure including a single, planar sensing structure formed from a layer of a quantum effect material.

Abstract: Some implementations described herein provide an optoelectronic device including a multi-layer photodiode structure. The multi-layer photodiode structure includes a stacked configuration of multiple sensing structures formed from quantum effect materials (e.g., a germanium material). By using the stacked configuration of multiple sensing structures, a quantum effect length is increased relative to another photodiode including a single layer photodiode structure. Furthermore, a lower sensing structure of the multi-layer sensing structure shares a substrate with integrated circuitry of the optoelectronic device. The lower sensing structure is electrically isolated from the integrated circuitry by doped isolation regions adjacent to sidewalls of the lower sensing structure.

Abstract: The present disclosure describes a structure with a substrate, a first interconnect region, a second interconnect region, and a memory device region. The first interconnect region is over the substrate and includes first interconnect structures. The second interconnect region is over the first interconnect region and includes second interconnect structures electrically connected to the first interconnect structures. Further, the memory device region is between the first and second interconnect regions and includes memory cells (e.g., ferroelectric random access memory (FeRAM) cells).

Abstract: A semiconductor structure and method for forming the semiconductor are provided. The semiconductor structure includes a logic device, a first contact connected to the logic device, a first power rail over the logic device and connected to the logic device, and a second power rail over the logic device. A transistor having a channel region including indium, gallium, zinc, and oxygen is over the second power rail and connected to the second power rail.

Abstract: Memory cells, semiconductor devices, semiconductor stacked structures, and fabrication methods are provided. An example memory cell includes a capacitor and a transistor stacked over the capacitor in a compact configuration. The capacitor includes a floating gate, a high-k dielectric layer, and a metal gate. The metal gate extends horizontally from a first sidewall to a second sidewall and vertically from a bottom surface to a top surface. The transistor includes the metal gate and a gate dielectric layer disposed on the metal gate. The gate dielectric layer includes two side portions respectively disposed on the two sidewalls of the metal gate and, and a top portion disposed on the top surface of the metal gate. The transistor further includes two separate S/D regions respectively formed on the two side portions of the gate dielectric layer, and a channel region formed on the top portion of the gate dielectric layer.

Abstract: A micromechanical arm array is provided. The micromechanical arm array comprises: a plurality of micromechanical arms spaced from each other in a first horizontal direction and extending in a second horizontal direction, wherein each micromechanical arm comprises a protrusion at a top of each micromechanical arm and protruding upwardly in a vertical direction; a plurality of protection films, each protection film encapsulating one of the plurality of micromechanical arms; and a metal connection structure extending in the first horizontal direction. The metal connection structure comprises: a plurality of joint portions, each joint portion corresponding to and surrounding the protrusion of one of the plurality of micromechanical arms; and a plurality of connection portions extending in the first horizontal direction and connecting two neighboring joint portions.

Abstract: A microdevice including a first pedestal, a second pedestal parallel to the first pedestal, the second pedestal comprising a first protrusion on its top surface. The device also including a conformal dielectric layer and a metal structure formed over a portion of the conformal dielectric layer. The metal structure including a first portion surrounding the first protrusion, a second portion parallel to the top surface of the polysilicon pedestal, and a third portion connecting the first portion and the second portion.

Abstract: The present disclosure describes a method for the formation of mirror micro-structures on radiation-sensing regions of image sensor devices. The method includes forming an opening within a front side surface of a substrate; forming a conformal implant layer on bottom and sidewall surfaces of the opening; growing a first epitaxial layer on the bottom and the sidewall surfaces of the opening; depositing a second epitaxial layer on the first epitaxial layer to fill the opening, where the second epitaxial layer forms a radiation-sensing region. The method further includes depositing a stack on exposed surfaces of the second epitaxial layer, where the stack includes alternating pairs of a high-refractive index material layer and a low-refractive index material layer.

Abstract: The present disclosure describes a method for the formation of mirror micro-structures on radiation-sensing regions of image sensor devices. The method includes forming an opening within a front side surface of a substrate; forming a conformal implant layer on bottom and sidewall surfaces of the opening; growing a first epitaxial layer on the bottom and the sidewall surfaces of the opening; depositing a second epitaxial layer on the first epitaxial layer to fill the opening, where the second epitaxial layer forms a radiation-sensing region. The method further includes depositing a stack on exposed surfaces of the second epitaxial layer, where the stack includes alternating pairs of a high-refractive index material layer and a low-refractive index material layer.

Abstract: A micromechanical arm array is provided. The micromechanical arm array comprises: a plurality of micromechanical arms spaced from each other in a first horizontal direction and extending in a second horizontal direction, wherein each micromechanical arm comprises a protrusion at a top of each micromechanical arm and protruding upwardly in a vertical direction; a plurality of protection films, each protection film encapsulating one of the plurality of micromechanical arms; and a metal connection structure extending in the first horizontal direction. The metal connection structure comprises: a plurality of joint portions, each joint portion corresponding to and surrounding the protrusion of one of the plurality of micromechanical arms; and a plurality of connection portions extending in the first horizontal direction and connecting two neighboring joint portions.

Abstract: A micromechanical arm array is provided. The micromechanical arm array comprises: a plurality of micromechanical arms spaced from each other in a first horizontal direction and extending in a second horizontal direction, wherein each micromechanical arm comprises a protrusion at a top of each micromechanical arm and protruding upwardly in a vertical direction; a plurality of protection films, each protection film encapsulating one of the plurality of micromechanical arms; and a metal connection structure extending in the first horizontal direction. The metal connection structure comprises: a plurality of joint portions, each joint portion corresponding to and surrounding the protrusion of one of the plurality of micromechanical arms; and a plurality of connection portions extending in the first horizontal direction and connecting two neighboring joint portions.

Abstract: The present disclosure describes a method for the formation of mirror micro-structures on radiation-sensing regions of image sensor devices. The method includes forming an opening within a front side surface of a substrate; forming a conformal implant layer on bottom and sidewall surfaces of the opening; growing a first epitaxial layer on the bottom and the sidewall surfaces of the opening; depositing a second epitaxial layer on the first epitaxial layer to fill the opening, where the second epitaxial layer forms a radiation-sensing region. The method further includes depositing a stack on exposed surfaces of the second epitaxial layer, where the stack includes alternating pairs of a high-refractive index material layer and a low-refractive index material layer.