Abstract: A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.

Abstract: An integrated circuit is provided which includes a first complementary field-effect transistor and a second complementary field-effect transistor. The first complementary field-effect transistor includes at least two first transistors respectively located on a first layer and a second layer. The second complementary field-effect transistor is disposed adjacent to the first complementary field-effect transistor. The second complementary field-effect transistor includes at least two second transistors respectively located on the first layer and the second layer. Type of one of the at least two first transistors located on the first layer is different from type of one of the at least two second transistors located on the first layer.

Abstract: A board-to-board connector includes an insulating body and a conductive terminal. The conductive terminal includes a mounting portion, a first resilient arm and a second resilient arm. The mounting portion includes a main body portion and at least one tab protruding from the main body portion. The first resilient arm includes a first connecting portion, a first elastic arm, a first contact portion, a first extension arm and a first end portion. The second resilient arm includes a second connecting portion, a second elastic arm, a second contact portion, a second extension arm and a second end portion. When the first circuit board and the second circuit board abut against the corresponding first contact portion and the second contact portion, the first extension arm is in contact with the second end portion and/or the second extension arm is in contact with the first end portion.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate including a base and a fin structure over the base. The fin structure includes a nanostructure. The semiconductor device structure includes a gate stack over the base and wrapped around the nanostructure. The gate stack has an upper portion and a sidewall portion, the upper portion is over the nanostructure, and the sidewall portion is over a first sidewall of the nanostructure. The semiconductor device structure includes a first inner spacer and a second inner spacer over opposite sides of the sidewall portion. A sum of a first width of the first inner spacer and a second width of the second inner spacer is greater than a third width of the sidewall portion as measured along a longitudinal axis of the fin structure.

Abstract: A method according to the present disclosure includes providing a workpiece including a first fin-shaped structure and a second fin-shaped structure over a substrate, depositing a nitride liner over the substrate and sidewalls of the first fin-shaped structure and the second fin-shaped structure, forming an isolation feature over the nitride liner and between the first fin-shaped structure and the second fin-shaped structure, epitaxially growing a cap layer on exposed surfaces of the first fin-shaped structure and the second fin-shaped structure and above the nitride liner, crystalizing the cap layer, and forming a first source/drain feature over a first source/drain region of the first fin-shaped structure and a second source/drain feature over a second source/drain region of the second fin-shaped structure.

Abstract: A computing system with graphics processor boosting is shown. The computing system has a graphics processing unit controlling a display, a code memory storing instructions, and a processor operating the graphics processing unit to control the display. The processor is configured to execute the instructions retrieved from the code memory to implement a plurality of graphics processor boosting modules for the graphics processing unit, and implement an activation controller that controls activation of the different graphics processor boosting modules through different configuration interfaces with balances between the different graphics processor boosting modules.

Abstract: A method for performing automatic activation control regarding VRS and associated apparatus are provided. The method applicable to a processing circuit may include: utilizing a rendering classifier to intercept at least one set of original graphic commands on a command path to obtain at least one rendering property, for classifying rendering corresponding to the at least one set of original graphic commands; utilizing the rendering classifier to classify the rendering into at least one predetermined rendering type among multiple predetermined rendering types according to the at least one rendering property, in order to determine at least one shading rate corresponding to the at least one predetermined rendering type for the rendering; and utilizing a shading rate controller to control the processing circuit to selectively activate a VRS function of the processing circuit, for rendering at the at least one shading rate corresponding to the at least one predetermined rendering type.

Abstract: A semiconductor device structure includes nanostructures formed over a substrate. The structure also includes a gate structure formed over and around the nanostructures. The structure also includes a spacer layer formed over a sidewall of the gate structure over the nanostructures. The structure also includes a source/drain epitaxial structure formed adjacent to the spacer layer. The structure also includes a contact structure formed over the source/drain epitaxial structure with an air spacer formed between the spacer layer and the contact structure.

Abstract: A semiconductor structure includes a via in contact with a conductive line and extending through a first etch stop layer, a first inter-metal dielectric layer, and a second etch stop layer. The second etch stop layer is disposed over the first inter-metal dielectric layer, and the first inter-metal dielectric layer is disposed over the first etch stop layer. The semiconductor structure also includes a trench in contact with the via and extending through an insulating layer and a second inter-metal dielectric layer. The second inter-metal dielectric layer is disposed over the insulating layer which is disposed over the second etch stop layer.

Abstract: An interconnect fabrication method is disclosed herein that utilizes a disposable etch stop hard mask over a gate structure during source/drain contact formation and replaces the disposable etch stop hard mask with a dielectric feature (in some embodiments, dielectric layers having a lower dielectric constant than a dielectric constant of dielectric layers of the disposable etch stop hard mask) before gate contact formation. An exemplary device includes a contact etch stop layer (CESL) having a first sidewall CESL portion and a second sidewall CESL portion separated by a spacing and a dielectric feature disposed over a gate structure, where the dielectric feature and the gate structure fill the spacing between the first sidewall CESL portion and the second sidewall CESL portion. The dielectric feature includes a bulk dielectric over a dielectric liner. The dielectric liner separates the bulk dielectric from the gate structure and the CESL.

Abstract: A semiconductor structure includes an epitaxial region having a front side and a backside. The semiconductor structure includes an amorphous layer formed over the backside of the epitaxial region, wherein the amorphous layer includes silicon. The semiconductor structure includes a first silicide layer formed over the amorphous layer. The semiconductor structure includes a first metal contact formed over the first silicide layer.

Abstract: A semiconductor interconnect structure includes a conductive line electrically coupled to an active semiconductor device, a first etch stop layer formed over the conductive line, a first dielectric layer formed over the first etch stop layer, a second etch stop layer formed over the first dielectric layer, a second dielectric layer formed over the second etch stop layer, and an interconnect structure electrically coupled to the via and extending through the first etch stop layer, the first dielectric layer, the second etch stop layer, and the second dielectric layer. The interconnect structure includes a via extending through the first etch stop layer, the second etch stop layer, and the first dielectric layer and a trench extending through the second dielectric layer.

Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate.

Abstract: In some implementations, a control device may determine a spacing measurement in a first dimension between a wafer on a susceptor and a pre-heat ring of a semiconductor processing tool and/or a gapping measurement in a second dimension between the wafer and the pre-heat ring, using one or more images captured in situ during a process by at least one optical sensor. Accordingly, the control device may generate a command based on a setting associated with the process being performed by the semiconductor processing tool and the spacing measurement and/or the gapping measurement. The control device may provide the command to at least one motor to move the susceptor.

Abstract: A method includes simultaneously forming a first dummy gate stack and a second dummy gate stack on a first portion and a second portion of a protruding fin, simultaneously removing a first gate electrode of the first dummy gate stack and a second gate electrode of the second dummy gate stack to form a first trench and a second trench, respectively, forming an etching mask, wherein the etching mask fills the first trench and the second trench, patterning the etching mask to remove the etching mask from the first trench, removing a first dummy gate dielectric of the first dummy gate stack, with the etching mask protecting a second dummy gate dielectric of the second dummy gate stack from being removed, and forming a first replacement gate stack and a second replacement gate stack in the first trench and the second trench, respectively.

Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

Abstract: A polysilicon layer is formed over a substrate. The polysilicon layer is etched to form a dummy gate electrode having a top portion with a first lateral dimension and a bottom portion with a second lateral dimension. The first lateral dimension is greater than, or equal to, the second lateral dimension. The dummy gate electrode is replaced with a metal gate electrode.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain region formed in a semiconductor substrate, a source/drain contact structure formed over the source/drain region, and a silicide region formed between the source/drain region and the source/drain contact structure. The semiconductor device structure also includes a first insulating spacer surrounding and in direct contact with the source/drain contact structure and a second insulating spacer and a third insulating spacer respectively formed on two opposite sidewalls of the source/drain contact structure and in direct contact with an outer edge of the first insulating spacer. A first sidewall of the second insulating spacer and a second sidewall of the third insulating spacer are respectively aligned to two opposite side edges of the source/drain region.

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate over the fin; reducing a thickness of a lower portion of the dummy gate proximate to the isolation regions, where after reducing the thickness, a distance between opposing sidewalls of the lower portion of the dummy gate decreases as the dummy gate extends toward the isolation regions; after reducing the thickness, forming a gate fill material along at least the opposing sidewalls of the lower portion of the dummy gate; forming gate spacers along sidewalls of the dummy gate and along sidewalls of the gate fill material; and replacing the dummy gate with a metal gate.