Patents by Inventor Shih-Yuan Chen

Shih-Yuan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220309372
    Abstract: An electronic device includes a pair of depletion gates, an accumulation gate, and a conductive resonator. The depletion gates are spaced apart from each other. The accumulation gate is over the depletion gates. The conductive resonator is over the depletion gates and the accumulation gate. The conductive resonator includes a first portion, a second portion, and a third portion. The first portion and the second portion are on opposite sides of the accumulation gate. The third portion interconnects the first and second portions of the conductive resonator and across the depletion gates. A bottom surface of the first portion of the conductive resonator is lower than a bottom surface of the accumulation gate.
    Type: Application
    Filed: July 8, 2021
    Publication date: September 29, 2022
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jiun-Yun LI, Shih-Yuan CHEN, Yao-Chun CHANG, Ian HUANG, Chiung-Yu CHEN
  • Publication number: 20220310804
    Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a stack of channel structures over a base structure. The semiconductor device structure also includes a first epitaxial structure and a second epitaxial structure sandwiching the channel structures. The semiconductor device structure further includes a gate stack wrapped around each of the channel structures and a backside conductive contact connected to the second epitaxial structure. A first portion of the backside conductive contact is directly below the base structure, and a second portion of the backside conductive contact extends upwards to approach a bottom surface of the second epitaxial structure. In addition, the semiconductor device structure includes an insulating spacer between a sidewall of the base structure and the backside conductive contact.
    Type: Application
    Filed: March 25, 2021
    Publication date: September 29, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huan-Chieh SU, Chun-Yuan CHEN, Li-Zhen YU, Shih-Chuan CHIU, Cheng-Chi CHUANG, Chih-Hao WANG
  • Publication number: 20220301981
    Abstract: A die includes: a semiconductor substrate having a front side and an opposing backside; a dielectric structure including a substrate oxide layer disposed on the front side of the semiconductor substrate and interlayer dielectric (ILD) layers disposed on the substrate oxide layer; an interconnect structure disposed in the dielectric structure; a through-silicon via (TSV) structure extending in a vertical direction from the backside of the semiconductor substrate through the front side of the semiconductor substrate, such that a first end of the TSV structure is disposed in the interconnect structure; and a TSV barrier structure including a barrier line that contacts the first end of the TSV structure, and a first seal ring disposed in the substrate oxide layer and that that surrounds the TSV structure in a lateral direction perpendicular to the vertical direction.
    Type: Application
    Filed: September 10, 2021
    Publication date: September 22, 2022
    Inventors: Jen-Yuan CHANG, Chia-Ping Lai, Shih-Chang Chen, Tzu-Chung Tsai, Chien-Chang Lee
  • Publication number: 20220285029
    Abstract: A medication risk evaluation method and a medication risk evaluation device are provided. The medication risk evaluation method includes: obtaining first medication route information related to a first medicine combination in a medication database; obtaining second medication route information related to a second medicine combination in the medication database; obtaining overlapping medication information between the first medication route information and the second medication route information; determining whether the overlapping medication information meets a noise exclusion condition; and if the overlapping medication information meets the noise exclusion condition, establishing a risk evaluation model based on other medication route information in the medication database excluding the first medication route information, where the risk evaluation model is adapted to evaluate a risk of using at least one medicine in the medication database.
    Type: Application
    Filed: July 5, 2021
    Publication date: September 8, 2022
    Applicants: Acer Incorporated, National Yang Ming Chiao Tung University
    Inventors: Pei-Jung Chen, Tsung-Hsien Tsai, Liang-Kung Chen, Shih-Tsung Huang, Fei-Yuan Hsiao
  • Publication number: 20220285223
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a transistor, a conductive feature on the transistor, a dielectric layer over the conductive feature, and an electrical connection structure in the dielectric layer and on the conductive feature. The electrical connection structure includes a first grain of a first metal material and a first inhibition layer extending along a grain boundary of the first grain of the first metal material, the first inhibition layer is made of a second metal material, and the first metal material and the second metal material have different oxidation/reduction potentials.
    Type: Application
    Filed: May 23, 2022
    Publication date: September 8, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Chuan CHIU, Jia-Chuan YOU, Chia-Hao CHANG, Chun-Yuan CHEN, Tien-Lu LIN, Yu-Ming LIN, Chih-Hao WANG
  • Patent number: 11437280
    Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: September 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Ching Lee, Hsin-Han Tsai, Shih-Hang Chiu, Tsung-Ta Tang, Chung-Chiang Wu, Hung-Chin Chung, Hsien-Ming Lee, Da-Yuan Lee, Jian-Hao Chen, Chien-Hao Chen, Kuo-Feng Yu, Chia-Wei Chen, Chih-Yu Hsu
  • Publication number: 20220277984
    Abstract: A method includes forming a first conductive feature on a substrate, forming a via that contacts the first conductive feature, the via comprising a conductive material, performing a Chemical Mechanical Polishing (CMP) process to a top surface of the via, depositing an Interlayer Dielectric (ILD) layer on the via, forming a trench within the ILD layer to expose the via, and filling the trench with a second conductive feature that contacts the via, the second conductive feature comprising a same material as the conductive material.
    Type: Application
    Filed: May 16, 2022
    Publication date: September 1, 2022
    Inventors: Chun-Yuan Chen, Shih-Chuan Chiu, Jia-Chuan You, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin
  • Publication number: 20220278159
    Abstract: An image sensor device is provided. The image sensor device includes a semiconductor substrate having a front surface, a back surface opposite to the front surface, and a light-sensing region close to the front surface. The image sensor device includes an insulating layer covering the back surface and extending into the semiconductor substrate. The protection layer has a first refractive index, and the first refractive index is less than a second refractive index of the semiconductor substrate and greater than a third refractive index of the insulating layer, and the protection layer conformally and continuously covers the back surface and extends into the semiconductor substrate. The image sensor device includes a reflective structure surrounded by insulating layer in the semiconductor substrate.
    Type: Application
    Filed: May 18, 2022
    Publication date: September 1, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh FANG, Ming-Chi WU, Ji-Heng JIANG, Chi-Yuan WEN, Chien-Nan TU, Yu-Lung YEH, Shih-Shiung CHEN, Kun-Yu LIN
  • Patent number: 11406160
    Abstract: An apparatus for buffing a shoe part includes a housing adapted to be articulated around at least a portion of the footwear part. A rotating spindle is positioned in the housing and has a buffing surface for engagement with the footwear part. A carriage is slideably connected to the housing and holds the spindle such that the buffing surface can be moved closer to and further away from the footwear part. An actuator is in the housing and in contact with the carriage. The actuator applies force to the carriage to increase the force of the buffing surface onto the footwear part. A biasing member is in the housing and in contact with the carriage. The biasing member exerts force onto the carriage in a direction opposite the force exerted by the actuator.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: August 9, 2022
    Assignee: NIKE, Inc.
    Inventors: Dragan Jurkovic, Shih-Yuan Wu, Chia-Wei Chang, Wen-Ruei Chang, Chien-Chun Chen, Chang-Chu Liao, Chia-Hung Lin
  • Publication number: 20220246758
    Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.
    Type: Application
    Filed: April 15, 2022
    Publication date: August 4, 2022
    Applicant: eMemory Technology Inc.
    Inventors: Chih-Hsin Chen, Shih-Chen Wang, Tsung-Mu Lai, Wen-Hao Ching, Chun-Yuan Lo, Wei-Chen Chang
  • Patent number: 11398259
    Abstract: A memory cell array of a multi-time programmable non-volatile memory includes plural memory cells. The memory cell has the structure of 1T1C cell, 2T1C cell or 3T1C cell. Moreover, the floating gate transistors of the memory cells in different rows of the memory cell array are constructed in the same well region. Consequently, the chip size is reduced. Moreover, by providing proper bias voltages to the memory cell array, the program action, the erase action or the read action can be performed normally.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: July 26, 2022
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Chih-Hsin Chen, Chun-Yuan Lo, Shih-Chen Wang, Tsung-Mu Lai
  • Publication number: 20220216621
    Abstract: An antenna structure includes a patch antenna including two opposite edges, a microstrip line connected to the patch antenna, two first radiation assemblies respectively disposed on two sides of the patch antenna, two second radiation assemblies disposed under the two first radiation assemblies, a liquid crystal layer disposed between a first plane and a second plane, and a ground plane disposed under the two second radiation assemblies. The patch antenna, the microstrip line, and the two first radiation assemblies are located on the first plane, and each of the first radiation assemblies includes multiple separated first conductors. The two second radiation assemblies are located on the second plane, and each of the second radiation assemblies includes multiple separated second conductors. A projection of the two second radiation assemblies on the first plane, the two first radiation assemblies, and the two edges of the patch antenna collectively form two loops.
    Type: Application
    Filed: August 6, 2021
    Publication date: July 7, 2022
    Applicant: Au Optronics Corporation
    Inventors: Shih-Yuan Chen, Hsiu-Ping Liao, Chun-I Wu, Yi-Chen Hsieh, Yi-Hsiang Lai, Ching-Huan Lin, Chuang Yueh Lin
  • Publication number: 20220209093
    Abstract: A semiconductor device includes a substrate; a first thermoelectric conduction leg, disposed on the substrate, and doped with a first type of dopant; a second thermoelectric conduction leg, disposed on the substrate, and doped with a second type of dopant, wherein the first and second thermoelectric conduction legs are spatially spaced from each other but disposed along a common row on the substrate; and a first intermediate thermoelectric conduction structure, disposed on a first end of the second thermoelectric conduction leg, and doped with the first type of dopant.
    Type: Application
    Filed: January 7, 2022
    Publication date: June 30, 2022
    Inventors: Ming-Hsien TSAI, Shang-Ying TSAI, Fu-Lung HSUEH, Shih-Ming YANG, Jheng-Yuan WANG, Ming-De CHEN
  • Publication number: 20220208680
    Abstract: A semiconductor device includes a first chip package, a heat dissipation structure and an adapter. The first chip package includes a semiconductor die laterally encapsulated by an insulating encapsulant, the semiconductor die has an active surface and a back surface opposite to the active surface. The heat dissipation structure is connected to the chip package. The adapter is disposed over the first chip package and electrically connected to the semiconductor die.
    Type: Application
    Filed: March 17, 2022
    Publication date: June 30, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yuan Teng, Hung-Yi Kuo, Hao-Yi Tsai, Tin-Hao Kuo, Yu-Chia Lai, Shih-Wei Chen
  • Publication number: 20220208326
    Abstract: A method for calculating a high risk route of administration is provided. Multiple arrangement routes composed of every two medicines among multiple medicines included in a medical record database are listed. A risk value of each arrangement route is calculated by querying the medical record database based on a specified medication result. A risk score of each arrangement route is calculated according to the risk value, and the arrangement routes are sorted based on the risk scores. Starting from the arrangement route with the highest risk score, N arrangement routes are retrieved and a combination on N of the arrangement routes is performed to obtain multiple strung routes. The number of medicines included in each strung route matches a specified medication number.
    Type: Application
    Filed: July 7, 2021
    Publication date: June 30, 2022
    Applicants: Acer Incorporated, National Yang Ming Chiao Tung University
    Inventors: Pei-Jung Chen, Tsung-Hsien Tsai, Liang-Kung Chen, Shih-Tsung Huang, Fei-Yuan Hsiao
  • Publication number: 20220199555
    Abstract: An electronic device includes a substrate, a transistor, and a ring resonator. The transistor is over the substrate. The ring resonator is over the substrate and includes a conductive loop and an impedance matching element. The conductive loop overlaps with the transistor. The impedance matching element is on the conductive loop and electrically isolated from the transistor.
    Type: Application
    Filed: March 9, 2022
    Publication date: June 23, 2022
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Shih-Yuan CHEN, Jiun-Yun LI, Rui-Fu XU, Chiung-Yu CHEN, Ting-I YEH, Yu-Jui WU, Yao-Chun CHANG
  • Patent number: 11276653
    Abstract: An electronic device includes a substrate, a transistor, and a ring resonator. The transistor is over the substrate. The transistor is configured to generate a quantum dot. The ring resonator is over the substrate and includes a conductive loop and an impedance matching element. The conductive loop overlaps with the transistor. The impedance matching element is on the conductive loop and is configured to determine a resonance frequency of the ring resonator.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: March 15, 2022
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Shih-Yuan Chen, Jiun-Yun Li, Rui-Fu Xu, Chiung-Yu Chen, Ting-I Yeh, Yu-Jui Wu, Yao-Chun Chang
  • Publication number: 20210118826
    Abstract: An electronic device includes a substrate, a transistor, and a ring resonator. The transistor is over the substrate. The transistor is configured to generate a quantum dot. The ring resonator is over the substrate and includes a conductive loop and an impedance matching element. The conductive loop overlaps with the transistor. The impedance matching element is on the conductive loop and is configured to determine a resonance frequency of the ring resonator.
    Type: Application
    Filed: October 17, 2019
    Publication date: April 22, 2021
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Shih-Yuan CHEN, Jiun-Yun LI, Rui-Fu XU, Chiung-Yu CHEN, Ting-I YEH, Yu-Jui WU, Yao-Chun CHANG
  • Patent number: 10170820
    Abstract: A wireless communication circuit and an electronic device are provided. The wireless communication circuit used for an electronic device includes a wireless transceiver unit used to generate a transmitting signal, an impedance matching unit electronically coupled to the wireless transceiver unit, a coupling unit and a system grounding surface. The impedance matching unit includes at least one impedance, the impedance matching unit is used to convert the transmitting signal to a feeding signal according to the impedance value of at least one impedance. The coupling unit is electronically coupled to the impedance matching unit, to radiate the energy of the feeding signal. The system grounding surface is used to transmit a first electromagnetic wave signal via resonance on the plane of the system grounding surface after receiving the energy of the feeding signal.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: January 1, 2019
    Assignee: ASUSTeK COMPUTER INC.
    Inventors: Shih-Chia Chiu, Shih-Yuan Chen, Skye Hui-Hsin Wu, Chien-Hao Chiu, Wang-Ta Hsieh, Wei-Hsin Shih
  • Publication number: 20180322116
    Abstract: An interactive translation system includes a first headset device, a first wireless communication device, a second headset device, and a second wireless communication device. The first and second headset devices receive voices, convert the voices into audio signals, and then transmit the audio signals. The first headset and second headset devices further receive translated audio signals, convert the translated audio signals into translated voices and then outputs. The first and second wireless communication devices receive the audio signals, convert the audio signals into text signals, and transmit the text signals therebetween. The first and second wireless communication devices further translate the text signals to translated text signals, convert the translated text signals into translated audio signals, and send back to the first headset and second headset devices.
    Type: Application
    Filed: September 13, 2017
    Publication date: November 8, 2018
    Inventors: To-Teng HUANG, Shih-Yuan CHEN