Abstract: The present disclosure provides a method for overlay error correction. The method includes: obtaining an overlay error based on a lower-layer pattern and an upper-layer pattern of a wafer, wherein the lower-layer pattern is obtained by first fabrication equipment through which the wafer passes, and the upper-layer pattern is obtained by exposure equipment; generating a corrected overlay error based on the overlay error and fabrication processes performed on the wafer after the first fabrication equipment and prior to the exposure equipment; and adjusting the exposure equipment based on the corrected overlay error.

Abstract: A mark for overlay error measurement and overlay error measurement is provided. The mark includes a first pattern and a second pattern. The first pattern is disposed on a first surface of a substrate. The second pattern is disposed on a second surface of the substrate. The second surface of the substrate is opposite to the first surface of the substrate. The first pattern overlaps at least a portion of the second pattern, and the first pattern and the second pattern collaboratively define a first overlay error.

Abstract: A method for overlay error correction includes generating a first overlay error based on a first overlay mark, wherein the first overlay error is indicative of a misalignment between a lower pattern and an upper pattern of the first overlay mark. The method also includes generating a second overlay error based on a second overlay mark, in response to an abnormal of the first overlay error is detected. The method further includes determining whether the abnormal of the first overlay error is caused by the misalignment between the lower pattern and the upper pattern depending on the second overlay error.

Abstract: A method for overlay error correction includes generating a first overlay error based on a first overlay mark, wherein the first overlay error is indicative of a misalignment between a lower pattern and an upper pattern of the first overlay mark. The method also includes generating a second overlay error based on a second overlay mark, in response to an abnormal of the first overlay error is detected. The method further includes determining whether the abnormal of the first overlay error is caused by the misalignment between the lower pattern and the upper pattern depending on the second overlay error.

Abstract: The present disclosure provides a method for overlay error correction. The method includes: obtaining an overlay error based on a lower-layer pattern and an upper-layer pattern of a wafer, wherein the lower-layer pattern is obtained by first fabrication equipment through which the wafer passes, and the upper-layer pattern is obtained by exposure equipment; generating a corrected overlay error based on the overlay error and fabrication processes performed on the wafer after the first fabrication equipment and prior to the exposure equipment; and adjusting the exposure equipment based on the corrected overlay error.

Abstract: The present disclosure provides a mark for overlay error measurement. The mark includes a first pattern and a second pattern. The first pattern is disposed on a substrate and at a first horizontal level. The first pattern includes a plurality of first sub-patterns and a plurality of second sub-patterns. The first sub-patterns extend along a first direction and are arranged along a second direction different from the first direction. The second sub-patterns are arranged along the second direction, wherein a profile of each of the plurality of first sub-patterns is different from a profile of each of the plurality of second sub-patterns. The second pattern is disposed at a second horizontal level different from the first horizontal level.

Abstract: A mark for overlay error measurement and overlay error measurement is provided. The mark includes a first pattern and a second pattern. The first pattern is disposed on a first surface of a substrate. The second pattern is disposed on a second surface of the substrate. The second surface of the substrate is opposite to the first surface of the substrate. The first pattern overlaps at least a portion of the second pattern, and the first pattern and the second pattern collaboratively define a first overlay error.

Abstract: A method of manufacturing a semiconductor device structure is provided. The method includes: providing a substrate; forming a photoresist layer on the substrate; patterning the photoresist layer to form a patterned photoresist layer; forming a pitch adjustment layer on the patterned photoresist layer to define a mask pattern; and determining whether the mask pattern meets a specification of semiconductor fabrication processes; when it is determined that the mask does not meet the specification of semiconductor fabrication processes, performing a rework operation to remove the pitch adjustment layer.