Abstract: A computer peripheral device is provided. The computer peripheral device is adapted to be installed in an electronic device supporting signal transmission of a first signal frequency. The computer peripheral device includes a human interface device (HID) and a bridging device. The HID includes a control unit to support signal transmission of a second signal frequency. The bridging device includes a first universal serial bus (USB) interface unit and a second USB interface unit. The first USB interface unit is adapted to be electrically connected to the electronic device, and supports signal transmission of the first signal frequency. The second USB interface unit is adapted to be electrically connected to the HID. The second USB interface unit regards the HID as a communication device class (CDC) device, instructs the control unit to generate an input signal at a timing corresponding to the first signal frequency, and transmits the input signal to the electronic device.

Abstract: A semiconductor structure includes an epitaxial region having a front side and a backside. The semiconductor structure includes an amorphous layer formed over the backside of the epitaxial region, wherein the amorphous layer includes silicon. The semiconductor structure includes a first silicide layer formed over the amorphous layer. The semiconductor structure includes a first metal contact formed over the first silicide layer.

Abstract: A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.

Abstract: A semiconductor structure includes an epitaxial region having a front side and a backside. The semiconductor structure includes an amorphous layer formed over the backside of the epitaxial region, wherein the amorphous layer includes silicon. The semiconductor structure includes a first silicide layer formed over the amorphous layer. The semiconductor structure includes a first metal contact formed over the first silicide layer.

Abstract: A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.

Abstract: A light source assembly is provided, including a substrate; a light-emitting element disposed on the substrate; and an optical film disposed on the light-emitting element. A diffuser layer is disposed between the optical film and the light-emitting element, wherein a haze of the diffuser layer is greater than 85%, a distance between the diffuser layer and the light-emitting element is in a range from 0 mm to 10 mm, and a thickness of the light-emitting element is less than the distance.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a stack of semiconductor nanostructures over a base structure and a first epitaxial structure and a second epitaxial structure sandwiching the semiconductor nanostructures. The semiconductor device structure also includes a gate stack wrapped around each of the semiconductor nanostructures and a backside conductive contact connected to the second epitaxial structure. A first portion of the backside conductive contact is directly below the base structure, and a second portion of the backside conductive contact extends upwards to approach a bottom surface of the second epitaxial structure. The semiconductor device structure further includes an insulating spacer between a sidewall of the base structure and the backside conductive contact.

Abstract: The present invention relates to an ethylene-vinyl alcohol copolymer composition, a single-layer film and a multilayer structure containing the same. Said ethylene-vinyl alcohol copolymer composition includes an ethylene-vinyl alcohol copolymer, an antioxidant, and a fluorine-containing compound; and the ratio of the antioxidant content to the fluorine content is 0.5 to 65. Thereby, the film containing said ethylene-vinyl alcohol copolymer composition not only has good heat resistance, but also can avoid the situation that a large number of gels are generated during the preparation process.

Abstract: The instant disclosure relates to saponified pellets of an ethylene-vinyl ester based copolymer as well as a film and a multilayer structure formed therefrom. The saponified pellets of an ethylene-vinyl ester based copolymer has an ethylene content of 24-35 mole %, and the pellets have a turbidity of less than 300 NTU when dissolved in a 60% (w/w) methanol aqueous solution; or the pellet has an ethylene content of 36-48 mole %, and the pellets have a turbidity of less than 200 NTU when dissolved in a 80% (w/w) methanol aqueous solution. The present invention controls the amount of aggregates by controlling the turbidity of the saponified pellets of an ethylene-vinyl ester based copolymer dissolved in methanol aqueous to reduce the amount of gel produced after film formation.

Abstract: Provided is an ethylene-vinyl alcohol copolymer composition having improved oxygen barrier properties, wherein the ethylene-vinyl alcohol copolymer composition comprises an ethylene-vinyl alcohol copolymer; and a manganese content of about 0.01 ppm to 0.49 ppm.

Abstract: The instant disclosure relates to ethylene vinyl alcohol copolymer resin composition and/or pellets thereof including one or more fluorine-containing micro-particles. The ethylene vinyl alcohol copolymer resin compositions and/or pellets thereof may have a melting pressure of 1.7 to 7.0 MPa at a shear rate of 20 s?1 and a melting point temperature of 190° C. EVOH films formed from the EVOH may have a Charpy impact strength of at least 2.3 KJ/m2 according to ISO 179-1 at 23° C. and an elongation at break of at least 17.8% according to ISO 527-2 at 23° C.

Abstract: A data driver for a display device comprises a first boost circuit, a first gate clock generation circuit, a first level shift circuit, and a data drive circuit. The first boost circuit is used to receive a supply voltage value and generate at least one preset voltage value. The first gate clock generation circuit is electrically coupled to the first boost circuit, and is used to receive a plurality of timing signals and at least one preset voltage value, and generate at least one first timing signal. The first level shift circuit is used to receive the at least one first timing signal and generate at least one gate timing signal. The data drive circuit is used to receive the timing signals, and generate a plurality of display data signals.

Abstract: A data driver for a display device comprises a first boost circuit, a first gate clock generation circuit, a first level shift circuit, and a data drive circuit. The first boost circuit is used to receive a supply voltage value and generate at least one preset voltage value. The first gate clock generation circuit is electrically coupled to the first boost circuit, and is used to receive a plurality of timing signals and at least one preset voltage value, and generate at least one first timing signal. The first level shift circuit is used to receive the at least one first timing signal and generate at least one gate timing signal. The data drive circuit is used to receive the timing signals, and generate a plurality of display data signals.

Abstract: A gate driver and a liquid crystal display using the same are provided. The gate driver includes a scan signal generating unit and a compensation unit. The scan signal generating unit has a plurality of output channels, and is used for sequentially outputting a scan signal through the output channels according to a basic clock and a start pulse. The compensation unit is coupled to the scan signal generating unit, and used for compensating the total resistance of each of the output channels, and sequentially receiving and transmitting the scan signal to a display panel.

Abstract: A gate driver and a liquid crystal display using the same are provided. The gate driver includes a scan signal generating unit and a compensation unit. The scan signal generating unit has a plurality of output channels, and is used for sequentially outputting a scan signal through the output channels according to a basic clock and a start pulse. The compensation unit is coupled to the scan signal generating unit, and used for compensating the total resistance of each of the output channels, and sequentially receiving and transmitting the scan signal to a display panel.

Abstract: A gate driver and a liquid crystal display using the same are provided. The gate driver includes a scan signal generating unit and a compensation unit. The scan signal generating unit has a plurality of output channels, and is used for sequentially outputting a scan signal through the output channels according to a basic clock and a start pulse. The compensation unit is coupled to the scan signal generating unit, and used for compensating the total resistance of each of the output channels, and sequentially receiving and transmitting the scan signal to a display panel.

Abstract: A gate driver and a liquid crystal display using the same are provided. The gate driver includes a scan signal generating unit and a compensation unit. The scan signal generating unit has a plurality of output channels, and is used for sequentially outputting a scan signal through the output channels according to a basic clock and a start pulse. The compensation unit is coupled to the scan signal generating unit, and used for compensating the total resistance of each of the output channels, and sequentially receiving and transmitting the scan signal to a display panel.

Abstract: A gate driver and a liquid crystal display using the same are provided. The gate driver includes a scan signal generating unit and a compensation unit. The scan signal generating unit has a plurality of output channels, and is used for sequentially outputting a scan signal through the output channels according to a basic clock and a start pulse. The compensation unit is coupled to the scan signal generating unit, and used for compensating the total resistance of each of the output channels, and sequentially receiving and transmitting the scan signal to a display panel.

Abstract: An exemplary control method of an output signal (e.g., from a timing controller in a flat panel display device) is adapted to be operative with a first signal with multiple pulses. In the control method, during a first time segment including part of the pulses of the first signal, a first enable signal is provided passing through a transmission path after a first time length from a rising edge of each of the part of the pulses. During a second time segment including another part of the pulses of the first signal, a second enable signal is provided passing through a part of the transmission path after a second time length from a rising edge of each of the another part of the pulses. The first time length is shorter than the second time length.

Abstract: An exemplary gate output control method includes the following steps: providing a gate control signal; using an angling control signal to angling modulate the gate control signal so as to generate a modulated gate control signal; and supplying the modulated gate control signal to a first integrated gate driver circuit and a second integrated gate driver circuit, to sequentially control the gate outputs of the first integrated gate driver circuit and the second integrated gate driver circuit. A duty ratio used by the angling control signal at the time of modulating the gate control signal to generate the modulated gate control signal for the first integrated gate driver circuit is different from another duty ratio used by the angling control signal at the time of modulating the gate control signal to generate the modulated gate control signal for the second integrated gate driver circuit.