Abstract: An integrated circuit (IC) may include a plurality of functional blocks, and each functional block of the plurality of functional blocks may include hardware circuits, wherein the plurality of functional blocks may include a first functional block. In addition, the first functional block may include a first macro circuit that is positioned within a first sub-region of the first functional block, wherein among multiple sides of the first sub-region, a first side of the first sub-region is closest to a boundary of the first functional block. Additionally, a first intermediate sub-region of the first functional block is positioned between the first side of the first sub-region and the boundary of the first functional block, and there is no tap cell in the first intermediate sub-region of the first functional block.

Abstract: A clock gating cell is provided. The clock gating cell includes an input stage and an output stage. The input stage receives a first clock signal and at least one input enable signal and generates a first enable signal corresponding to one of the least one input enable signal according to the first clock signal. The output stage is coupled to the input stage. The output stage receives the first enable signal and the first clock signal and generates a clock gating signal according to the first enable signal and the first clock signal. The input stage operates based on a first voltage threshold, and the output stage operates based on a second voltage threshold. The first voltage threshold is different from the second voltage threshold.

Abstract: The present disclosure discloses a set of novel epigenetic biomarkers for early detection, prediction of treatment response and prognosis of colorectal cancer. Aberrant methylation of the epigenetic biomarkers can be detected in tumor tissues and plasma samples from colorectal cancer patients but not in normal individuals. The present disclosure also discloses primers and probes used herein.

Abstract: A clock gating cell is provided. The clock gating cell includes an input stage and an output stage. The input stage receives a first clock signal and at least one input enable signal and generates a first enable signal corresponding to one of the least one input enable signal according to the first clock signal. The output stage is coupled to the input stage. The output stage receives the first enable signal and the first clock signal and generates a clock gating signal according to the first enable signal and the first clock signal. The input stage operates based on a first voltage threshold, and the output stage operates based on a second voltage threshold. The first voltage threshold is different from the second voltage threshold.

Abstract: A millimeter wave radar apparatus determining an obstacle on a railway is applied to the railway and the obstacle. The millimeter wave radar apparatus includes a user interface and a millimeter wave radar. The user interface is configured to control the millimeter wave radar. The millimeter wave radar is configured to transmit a radar wave to a predetermined range on the railway. The millimeter wave radar is configured to receive a reflected radar wave reflected from the predetermined range on the railway based on the radar wave. The user interface is configured to determine whether the obstacle is in the predetermined range on the railway based on the reflected radar wave. If the user interface determines that the obstacle is in the predetermined range on the railway, the user interface is configured to provide a warning.

Abstract: An integrated circuit (IC) may include a plurality of functional blocks, and each functional block of the plurality of functional blocks may include hardware circuits, wherein the plurality of functional blocks may include a first functional block. In addition, the first functional block may include a first macro circuit that is positioned within a first sub-region of the first functional block, wherein among multiple sides of the first sub-region, a first side of the first sub-region is closest to a boundary of the first functional block. Additionally, a first intermediate sub-region of the first functional block is positioned between the first side of the first sub-region and the boundary of the first functional block, and there is no tap cell in the first intermediate sub-region of the first functional block.

Abstract: A system and a method for estimating the mechanical behavior of human lower limbs is provided. The method includes the following steps: sensing a plurality of foot pressure signals of a user by using a sensor array, the foot pressure signals comprising at least a rearfoot pressure signal and at least a forefoot pressure signal; calculating a temporal sequence of a gait cycle of the user according to the foot pressure signals; calculating a foot reaction force of the user according to the foot pressure signals and a calibration parameter; and calculating a mechanical state of the lower limb joints of the user according to the temporal sequence of the gait cycle and the foot reaction force.

Abstract: A system and a method for estimating the mechanical behavior of human lower limbs is provided. The method includes the following steps: sensing a plurality of foot pressure signals of a user by using a sensor array, the foot pressure signals comprising at least a rearfoot pressure signal and at least a forefoot pressure signal; calculating a temporal sequence of a gait cycle of the user according to the foot pressure signals; calculating a foot reaction force of the user according to the foot pressure signals and a calibration parameter; and calculating a mechanical state of the lower limb joints of the user according to the temporal sequence of the gait cycle and the foot reaction force.

Abstract: The present invention provides a method for accessing a memory. The memory contains M one-time programmable memory blocks, and each has a first memory sector and a second memory sector. The method includes: selecting a first target memory block and reading the first target memory block. The step of selecting a first target memory block is performed by comparing the second memory sectors of N one-time programmable memory blocks from M one-time programmable memory blocks by following a search rule to select the first target memory block.

Abstract: The present invention provides a method for accessing a memory. The memory contains M one-time programmable memory blocks, and each has a first memory sector and a second memory sector. The method includes: selecting a first target memory block and reading the first target memory block. The step of selecting a first target memory block is performed by comparing the second memory sectors of N one-time programmable memory blocks from M one-time programmable memory blocks by following a search rule to select the first target memory block.

Abstract: A design method for full chip element on the memory, the method splits the elements in the Hard macro into the elements with transistor level for the automation design. In the situation when there are more than 2 high voltage circuits, the method provides multiple bypass circuits as the V SS and V DD, wherein the V SS and V DD are two powers that can be recognized by the software. The multiple high voltage circuits are used as the signal circuits for routing, so that the objective of running the auto-routing on all elements in the Hard macro can be achieved. The schematic design in the Hard macro is subsequently integrated into the other part to accomplish the full chip auto placement and routing.