Patents by Inventor Shih-Yun Lin

Shih-Yun Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11920157
    Abstract: Applications of butylidenephthalide (BP), comprising the use of BP in providing a kit for promoting differentiation of stem cells into brown adipose cells, and the use of BP in preparing a medicament, wherein the medicament is used for inhibiting the accumulation of white adipose cells, promoting the conversion of white adipose cells into brown adipose cells, inhibiting weight gain and/or reducing the content of triglycerides, glucose, and total cholesterol in blood.
    Type: Grant
    Filed: September 15, 2022
    Date of Patent: March 5, 2024
    Assignee: NATIONAL DONG HWA UNIVERSITY
    Inventors: Tzyy-Wen Chiou, Shinn-Zong Lin, Horng-Jyh Harn, Hong-Lin Su, Shih-Ping Liu, Kang-Yun Lu, Jeanne Hsieh
  • Publication number: 20230179206
    Abstract: A clock gating cell is provided. The clock gating cell includes an input stage and an output stage. The input stage receives a first clock signal and at least one input enable signal and generates a first enable signal corresponding to one of the least one input enable signal according to the first clock signal. The output stage is coupled to the input stage. The output stage receives the first enable signal and the first clock signal and generates a clock gating signal according to the first enable signal and the first clock signal. The input stage operates based on a first voltage threshold, and the output stage operates based on a second voltage threshold. The first voltage threshold is different from the second voltage threshold.
    Type: Application
    Filed: November 9, 2022
    Publication date: June 8, 2023
    Inventors: Kin-Hooi DIA, Ssu-Yen WU, Shih-Yun LIN
  • Publication number: 20230012128
    Abstract: A millimeter wave radar apparatus determining an obstacle on a railway is applied to the railway and the obstacle. The millimeter wave radar apparatus includes a user interface and a millimeter wave radar. The user interface is configured to control the millimeter wave radar. The millimeter wave radar is configured to transmit a radar wave to a predetermined range on the railway. The millimeter wave radar is configured to receive a reflected radar wave reflected from the predetermined range on the railway based on the radar wave. The user interface is configured to determine whether the obstacle is in the predetermined range on the railway based on the reflected radar wave. If the user interface determines that the obstacle is in the predetermined range on the railway, the user interface is configured to provide a warning.
    Type: Application
    Filed: July 11, 2021
    Publication date: January 12, 2023
    Inventors: Chun-Chi KO, Shih-Yun LIN, Tsai-Ling YU
  • Publication number: 20220366116
    Abstract: An integrated circuit (IC) may include a plurality of functional blocks, and each functional block of the plurality of functional blocks may include hardware circuits, wherein the plurality of functional blocks may include a first functional block. In addition, the first functional block may include a first macro circuit that is positioned within a first sub-region of the first functional block, wherein among multiple sides of the first sub-region, a first side of the first sub-region is closest to a boundary of the first functional block. Additionally, a first intermediate sub-region of the first functional block is positioned between the first side of the first sub-region and the boundary of the first functional block, and there is no tap cell in the first intermediate sub-region of the first functional block.
    Type: Application
    Filed: February 16, 2022
    Publication date: November 17, 2022
    Applicant: MEDIATEK INC.
    Inventors: Yu-Tung Chang, Yi-Chun Tsai, Tung-Kai Tsai, Yi-Te Chiu, Shih-Yun Lin, Hung-Ming Chu, Yi-Feng Chen
  • Patent number: 9521964
    Abstract: A system and a method for estimating the mechanical behavior of human lower limbs is provided. The method includes the following steps: sensing a plurality of foot pressure signals of a user by using a sensor array, the foot pressure signals comprising at least a rearfoot pressure signal and at least a forefoot pressure signal; calculating a temporal sequence of a gait cycle of the user according to the foot pressure signals; calculating a foot reaction force of the user according to the foot pressure signals and a calibration parameter; and calculating a mechanical state of the lower limb joints of the user according to the temporal sequence of the gait cycle and the foot reaction force.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: December 20, 2016
    Assignee: Industrial Technology Research Institute
    Inventors: Shih-Yun Lin, Chi-Kang Wu, Chih-Hung Huang, Chueh-Shan Liu
  • Publication number: 20130165820
    Abstract: A system and a method for estimating the mechanical behavior of human lower limbs is provided. The method includes the following steps: sensing a plurality of foot pressure signals of a user by using a sensor array, the foot pressure signals comprising at least a rearfoot pressure signal and at least a forefoot pressure signal; calculating a temporal sequence of a gait cycle of the user according to the foot pressure signals; calculating a foot reaction force of the user according to the foot pressure signals and a calibration parameter; and calculating a mechanical state of the lower limb joints of the user according to the temporal sequence of the gait cycle and the foot reaction force.
    Type: Application
    Filed: July 31, 2012
    Publication date: June 27, 2013
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Shih-Yun Lin, Chi-Kang Wu, Chih-Hung Huang, Chueh-Shan Liu
  • Patent number: 7254086
    Abstract: The present invention provides a method for accessing a memory. The memory contains M one-time programmable memory blocks, and each has a first memory sector and a second memory sector. The method includes: selecting a first target memory block and reading the first target memory block. The step of selecting a first target memory block is performed by comparing the second memory sectors of N one-time programmable memory blocks from M one-time programmable memory blocks by following a search rule to select the first target memory block.
    Type: Grant
    Filed: October 19, 2005
    Date of Patent: August 7, 2007
    Assignee: eMemory Technology Inc.
    Inventors: Ching-Yuan Lin, Hong-Yi Liao, Yen-Tai Lin, Shih-Yun Lin, Chun-Hung Lu
  • Publication number: 20060262626
    Abstract: The present invention provides a method for accessing a memory. The memory contains M one-time programmable memory blocks, and each has a first memory sector and a second memory sector. The method includes: selecting a first target memory block and reading the first target memory block. The step of selecting a first target memory block is performed by comparing the second memory sectors of N one-time programmable memory blocks from M one-time programmable memory blocks by following a search rule to select the first target memory block.
    Type: Application
    Filed: October 19, 2005
    Publication date: November 23, 2006
    Inventors: Ching-Yuan Lin, Hong-Yi Liao, Yen-Tai Lin, Shih-Yun Lin, Chun-Hung Lu
  • Publication number: 20030208738
    Abstract: A design method for full chip element on the memory, the method splits the elements in the Hard macro into the elements with transistor level for the automation design. In the situation when there are more than 2 high voltage circuits, the method provides multiple bypass circuits as the V SS and V DD, wherein the V SS and V DD are two powers that can be recognized by the software. The multiple high voltage circuits are used as the signal circuits for routing, so that the objective of running the auto-routing on all elements in the Hard macro can be achieved. The schematic design in the Hard macro is subsequently integrated into the other part to accomplish the full chip auto placement and routing.
    Type: Application
    Filed: April 24, 2002
    Publication date: November 6, 2003
    Inventors: Yu-Ming Hsu, Yen-Yai Lin, Shih-Yun Lin