Abstract: A dual-speed, dual format full-duplex two-wire voiceband data transmission system provides automatic speed selection at the answering terminal responsive to a handshaking sequence which is compatible with existing systems operating at telegraph speeds. Existing systems provide asynchronous full-duplex serial data transmission in the speed range of zero to 300 bits per second using frequency-shift keying of tones in split frequency bands dedicated to the respective transmisson directions. Alternative full-duplex serial data transmission at 1200 bits per second using phase-shift keying of carrier waves in these same split frequency bands can now be provided from a common line protocol.

Abstract: Asynchronous character-oriented (start-stop) data are transmitted through a synchronous transmission channel at a rate which can exceed the synchronous rate. The excess data rate is accomplished in an input buffer at the transmitter by suppressing occasional stop bits in proportion to the difference between synchronous and asynchronous rates. An output buffer at the receiver detects start bits and thereafter monitors the presence or absence of stop bits. When a stop bit is absent, the output buffer restores it before delivering the character to the data user.Special control signals not organized into characters, such as, all-space signals are also monitored at both transmitter and receiver to insure that stop bits are not spuriously inserted.

Abstract: A demodulator for differentially coherent phase-shift keyed data signals correlates samples taken in consecutive baud intervals. Depending on the results of at least two such correlations or lack thereof, counts are registered in unidirectional counters supplied with thresholds related to preassigned counts per baud interval. Bistable circuits respond to the attainment, or failure of attainment, of the threshold-count levels during each baud interval, after which the counters are reset to a reference level. The states of the bistable circuits directly represent binary data without further logic operations in the four-phase case particularly.

Abstract: A full duplex, synchronous data set (10) includes primary signal processing circuitry which generates a modulated transmit data signal in response to serial data from a terminal interface (17). The modulated data signal is transmitted over a primary channel of a transmit line (11). The primary signal processing circuitry also receives modulated data signals from a primary channel of a receive line (12) and recovers therefrom a serial bit stream for presentation to the interface. The operating parameters of the primary signal processing circuitry are specified by a primary controller (30) over a plurality of buses (PA, PC, PD). The primary controller includes a microprocessor (310) and associated peripherals (315, 320, 325, 330, 335). The data set also includes secondary signal processing circuitry (40) which transmits and receives diagnostic and control information over respective secondary channels of the transmit line and receive lines.