Patents by Inventor Shiho Moriai

Shiho Moriai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7822196
    Abstract: It is desired to share one circuit by an encryption unit 200 and a decryption unit 500. A normal data transformation unit (FL) 251 and an inverse data transformation unit (FL?1) 273 are located at point symmetry on a non-linear data transformation unit 220, and a normal data transformation unit (FL) 253 and an inverse data transformation unit (FL?1) 271 are located at point symmetry on the non-linear data transformation unit 220. Therefore, the encryption unit 200 and the decryption unit 500 can be configured using the same circuits.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: October 26, 2010
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Nippon Telegraph and Telephone Corporation
    Inventors: Mitsuru Matsui, Toshio Tokita, Junko Nakajima, Masayuki Kanda, Shiho Moriai, Kazumaro Aoki
  • Publication number: 20100262312
    Abstract: An electric power apparatus includes an energy device, a device manager, and a storage system manager.
    Type: Application
    Filed: March 25, 2010
    Publication date: October 14, 2010
    Applicant: SONY CORPORATION
    Inventors: Eiichiro Kubota, Shiho Moriai
  • Patent number: 7761707
    Abstract: To provide a recording medium on which an entire piece of decryption information that is required to be highly secure is recorded while being kept secure even when it is larger in data size than the storage capacity of an area originally intended for recording it. A recording medium in which encrypted content that has been encrypted and decryption information for the decryption of the encrypted content are recorded in two areas of different security levels. Decryption information B which is a portion of the decryption information is recorded in an area L of a relatively higher security level. The encrypted content and decryption information C which is the remainder of the decryption information that has been encrypted are recorded in an area D of a relatively lower security level. The decryption information B recorded in the area L includes information indicating the location where the decryption information C is recorded and information for the decryption of the remainder.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: July 20, 2010
    Assignee: Sony Computer Entertainment Inc.
    Inventors: Muneki Shimada, Shiho Moriai, Kazuhiro Kanee
  • Patent number: 7760871
    Abstract: It is desired to share one circuit by an encryption unit 200 and a decryption unit 500. A normal data transformation unit (FL) 251 and an inverse data transformation unit (FL?1) 273 are located at point symmetry on a non-linear data transformation unit 220, and a normal data transformation unit (FL) 253 and an inverse data transformation unit (FL?1) 271 are located at point symmetry on the non-linear data transformation unit 220. Therefore, the encryption unit 200 and the decryption unit 500 can be configured using the same circuits.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: July 20, 2010
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Nippon Telegraph and Telephone Corporation
    Inventors: Mitsuru Matsui, Toshio Tokita, Junko Nakajima, Masayuki Kanda, Shiho Moriai, Kazumaro Aoki
  • Patent number: 7760870
    Abstract: It is desired to share one circuit by an encryption unit 200 and a decryption unit 500. A normal data transformation unit (FL) 251 and an inverse data transformation unit (FL?1) 273 are located at point symmetry on a non-linear data transformation unit 220, and a normal data transformation unit (FL) 253 and an inverse data transformation unit (FL?1) 271 are located at point symmetry on the non-linear data transformation unit 220. Therefore, the encryption unit 200 and the decryption unit 500 can be configured using the same circuits.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: July 20, 2010
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Nippon Telegraph and Telephone Corporation
    Inventors: Mitsuru Matsui, Toshio Tokita, Junko Nakajima, Masayuki Kanda, Shiho Moriai, Kazumaro Aoki
  • Publication number: 20100104093
    Abstract: A common-key blockcipher processing configuration with enhanced immunity against attacks such as saturation attacks and algebraic attacks (XSL attacks) is realized. In an encryption processing apparatus that performs common-key blockcipher processing, S-boxes serving as non-linear transformation processing parts set in round-function executing parts are configured using at least two different types of S-boxes. With this configuration, the immunity against saturation attacks can be enhanced. Also, types of S-boxes present a mixture of different types. With this configuration, the immunity against algebraic attacks (XSL attacks) can be enhanced, thereby realizing a highly secure encryption processing apparatus.
    Type: Application
    Filed: August 29, 2007
    Publication date: April 29, 2010
    Inventors: Taizo Shirai, Kyoji Shibutani, Toru Akishita, Shiho Moriai
  • Publication number: 20100091991
    Abstract: A configuration that efficiently executes cryptographic processing to which a plurality of different F-functions are applied is provided. In a configuration that executes cryptographic processing by performing round operations to which different F-functions are selectively applied, a plurality of F-function correspondence tables, each corresponding to one of the F-functions, in which input values and output values or intermediate values are associated with each other are stored in a memory; in accordance with a prescribed cryptographic processing sequence, addresses corresponding to F-functions for the respective rounds are applied to read F-function correspondence tables from the memory; and output values or intermediate values for input values are acquired on the basis of reference to the tables to obtain data transformation results in accordance with the respective F-functions.
    Type: Application
    Filed: August 29, 2007
    Publication date: April 15, 2010
    Inventors: Kyoji Shibutani, Taizo Shirai, Toru Akishita, Shiho Moriai
  • Patent number: 7697684
    Abstract: It is desired to share one circuit by an encryption unit 200 and a decryption unit 500. A normal data transformation unit (FL) 251 and an inverse data transformation unit (FL?1) 273 are located at point symmetry on a non-linear data transformation unit 220, and a normal data transformation unit (FL) 253 and an inverse data transformation unit (FL?1) 271 are located at point symmetry on the non-linear data transformation unit 220. Therefore, the encryption unit 200 and the decryption unit 500 can be configured using the same circuits.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: April 13, 2010
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Nippon Telegraph and Telephone Corporation
    Inventors: Mitsuru Matsui, Toshio Tokita, Junko Nakajima, Masayuki Kanda, Shiho Moriai, Kazumaro Aoki
  • Publication number: 20100024029
    Abstract: An authentication requesting device which includes a battery connecting section to be connected to a battery and a receiving section to be supplied with power from an external power source when connected to the external power source, and executes an authentication process for authenticating a battery connected to the battery connecting section, where the authentication requesting device is arranged to change the authentication process depending on whether or not the receiving section is being supplied with power from the external power source.
    Type: Application
    Filed: September 30, 2009
    Publication date: January 28, 2010
    Applicant: Sony Computer Entertainment Inc.
    Inventors: Dai Sasaki, Shiho Moriai
  • Publication number: 20100014664
    Abstract: To realize a common-key block cipher process configuration with increased difficulty of key analysis and improved security. In a configuration for storing in a register an intermediate key generated by using a secret key transformation process and performing a transformation process on the register-stored data to generate a round key, a process of swapping (permuting) data segments constituting the register-stored data is executed to generate a round key. For example, four data segments are produced so that two sets of data segments having an equal number of bits are set, and a process of swapping the individual data segments is repeatedly executed to generate a plurality of different round keys. With this configuration, the bit array of each round key can be effectively permuted, and round keys with low relevance can be generated. A high-security cryptographic process with increased difficulty of key analysis can be realized.
    Type: Application
    Filed: November 21, 2007
    Publication date: January 21, 2010
    Inventors: Taizo Shirai, Kyoji Shibutani, Toru Akishita, Shiho Moriai
  • Publication number: 20100014659
    Abstract: In extended Feistel type common key block cipher processing, a configuration is realized in which an encryption function and a decryption function are commonly used. In a cryptographic processing configuration to which an extended Feistel structure in which the number of data lines d is set to an integer satisfying d?3 is applied, involution properties, that is, the application of a common function to encryption processing and decryption processing, can be achieved. With a configuration in which round keys are permuted or F-functions are permuted in the decryption processing, processing using a common function can be performed by setting swap functions for the encryption processing and the decryption processing to have the same processing style.
    Type: Application
    Filed: August 29, 2007
    Publication date: January 21, 2010
    Inventors: Kyoji Shibutani, Toru Akishita, Shiho Moriai
  • Publication number: 20100008498
    Abstract: A common-key blockcipher processing structure that makes analysis of key more difficult and enhances security and implementation efficiency is realized. In a key scheduling part in an encryption processing apparatus that performs common-key blockcipher processing, a secret key is input to an encryption function including a round function employed in an encryption processing part to generate an intermediate key, and the result of performing bijective transformation based on the intermediate key, the secret key, and the like and the result of performing an exclusive-OR operation on the bijective-transformed data are applied to round keys. With this structure, generation of round keys based on the intermediate key generated using the encryption function whose security has been ensured is performed, thereby making it possible to make analysis of the keys more difficult. The structure of the key scheduling part can be simplified, thereby making it possible to improve the implementation efficiency.
    Type: Application
    Filed: August 29, 2007
    Publication date: January 14, 2010
    Inventors: Taizo Shirai, Kyoji Shibutani, Toru Akishita, Shiho Moriai
  • Publication number: 20100002872
    Abstract: A non-linear transformation processing structure having a high implementation efficiency and a high security is realized. Data transformation is performed using a first non-linear transformation part performing non-linear transformation using a plurality of small S-boxes; a linear transformation part receiving all the outputs from the first non-linear transformation part and performing data transformation using a matrix for performing optimal diffusion mappings; and a second non-linear transformation part including a plurality of small non-linear transformation parts that perform non-linear transformation on individual data units into which output data from the linear transformation part is divided. With this structure, appropriate data diffusion can be achieved without excessively increasing a critical path, and a structure with a high implementation efficiency and a high security can be achieved.
    Type: Application
    Filed: August 29, 2007
    Publication date: January 7, 2010
    Inventors: Kyoji Shibutani, Taizo Shirai, Toru Akishita, Shiho Moriai
  • Patent number: 7617395
    Abstract: A peripheral device that is connected to a main body as an authentication requesting device operates as a device to be authenticated. Receiving code-related information from the main body, the peripheral device acquires a challenge code on the basis of the received code-related information, generates encrypted information by encrypting the challenge code, and transmits encryption-related information that relates to the generated encrypted information to the main body. The code-related information is part of the challenge code and/or the encryption-related information is part of the encrypted information.
    Type: Grant
    Filed: November 21, 2005
    Date of Patent: November 10, 2009
    Assignee: Sony Computer Entertainment Inc.
    Inventors: Dai Sasaki, Shiho Moriai
  • Publication number: 20080256401
    Abstract: The present invention is directed to an information processing system composed of plural information processing units adapted for mutually executing data communication, and for executing data processing in which communication data has been applied. The first entity A transmits error notification data on the basis of error detection to execute initial state return processing on the condition that data reception after error notification data has been transmitted is made, and the second entity B transmits error notification data on the basis of error detection to execute initial state return processing on the condition that transmit processing of error notification data is executed. Thus, the both entities A and B can return to the initial state in a manner synchronous with each other. As a result, it becomes possible to perform reliable error recovery and data processing restart.
    Type: Application
    Filed: November 15, 2005
    Publication date: October 16, 2008
    Applicants: Sony Corporation, Sony Computer Entertainment Inc.
    Inventors: Masafumi Kusakawa, Sumio Morioka, Muneki Shimada, Shiho Moriai, Dai Sasaki
  • Publication number: 20080056490
    Abstract: An encryption processing apparatus for performing common-key blockcipher processing, the encryption processing apparatus includes an encryption processing part that performs data transformation in which a round function is iterated for a plurality of rounds; and a key scheduling part that generates round keys used to execute the round function. The key scheduling part is configured to repeatedly apply an xs times multiplication over an extension field GF( 2m), generated by an m-th order irreducible polynomial f(x) defined over GF(2), to an m-bit intermediate key generated by transformation of a secret key to generate a plurality of different round intermediate keys serving as data for generating a plurality of different round keys.
    Type: Application
    Filed: August 29, 2007
    Publication date: March 6, 2008
    Inventors: Toru Akishita, Taizo Shirai, Kyoji Shibutani, Shiho Moriai
  • Publication number: 20080016342
    Abstract: To provide a recording medium on which an entire piece of decryption information that is required to be highly secure is recorded while being kept secure even when it is larger in data size than the storage capacity of an area originally intended for recording it. A recording medium in which encrypted content that has been encrypted and decryption information for the decryption of the encrypted content are recorded in two areas of different security levels. Decryption information B which is a portion of the decryption information is recorded in an area L of a relatively higher security level. The encrypted content and decryption information C which is the remainder of the decryption information that has been encrypted are recorded in an area D of a relatively lower security level. The decryption information B recorded in the area L includes information indicating the location where the decryption information C is recorded and information for the decryption of the remainder.
    Type: Application
    Filed: March 23, 2005
    Publication date: January 17, 2008
    Inventors: Muneki Shimada, Shiho Moriai, Kazuhiro Kanee
  • Publication number: 20070294535
    Abstract: Provided is an authentication system capable of identifying a cause of a failure when authentication fails. A data structure of data to be authenticated has a header authentication data area (D2), and an authentication data area (D4) in addition to a header area (D1) and a data area (D3). The header authentication data area (D2) authenticates validity of the header area (D1), and the authentication data area (D4) authenticates the validity of the header authentication header area (D2) and the data area (D3). Since two kinds of authentication are carried out, the cause of the failure in authentication can be identified easily when authentication is failed.
    Type: Application
    Filed: March 23, 2005
    Publication date: December 20, 2007
    Inventors: Shiho Moriai, Muneki Shimada, Kyoji Shibutani
  • Patent number: 7269529
    Abstract: A data processing apparatus that tests whether a secure circuit is normal or not while maintaining confidentiality of the secured circuit is provided: wherein the secured circuit conducts a self-diagnostic test thereof in accordance with a self-diagnostic test start instruction signal from a CPU, and the secured circuit outputs a self-diagnostic test result signal indicating whether the secured circuit is normal or not to the CPU.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: September 11, 2007
    Assignees: Sony Corporation, Sony Computer Entertainment Inc.
    Inventors: Masanobu Okabe, Masafumi Kusakawa, Kyoji Shibutani, Sumio Morioka, Asami Yoshida, Muneki Shimada, Shiho Moriai
  • Patent number: 7187769
    Abstract: In the evaluation of the randomness of an S-box, measures of resistance to higher order cryptanalysis, interpolation cryptanalysis, partitioning cryptanalysis and differential-linear cryptanalysis and necessary conditions for those measures to have resistance to each cryptanalysis are set, then for functions as candidates for the S-box, it is evaluated whether one or all of the conditions are satisfied, and those of the candidate functions for which one or all of the conditions are satisfied are selected as required. It is also possible to further evaluate the resistance of such selected functions to at least one of differential cryptanalysis and linear cryptanalysis and select those of the candidate functions which are resistant to at least one of the cryptanalyses as required.
    Type: Grant
    Filed: June 1, 1999
    Date of Patent: March 6, 2007
    Assignee: Nippon Telegraph and Telephone Public Corporation
    Inventors: Shiho Moriai, Kazumaro Aoki, Masayuki Kanda, Youichi Takashima, Kazuo Ohta