Abstract: A semiconductor device includes: a first cache that includes a first memory and rewrite flags that indicate whether rewriting has been performed for each piece of data held in the first memory; and a second cache that includes a second memory and a third memory that has a lower writing speed than the second memory, stores data evicted from the first cache in the second memory when a rewrite flag corresponding to the evicted data indicates a rewrite state, and stores data evicted from the first cache in the third memory when a rewrite flag corresponding to the evicted data indicates a non-rewrite state.

Abstract: A device including: a processor executing a program; a first cache memory; a second cache memory belonging to a memory hierarchy lower than that of the first cache memory; a determination unit that determines, based on first information indicating a virtual address of information accessed in the second cache memory when the program is executed, second information indicating a virtual address of target information to be prefetched; and a prefetch unit that prefetches the target information and stores the prefetched target information in the second cache memory, wherein the second cache memory includes a conversion unit that converts, by using correspondence information indicating a correspondence relationship between the physical address of the target information and the virtual address of the target information, the second information into third information indicating a physical address of the target information, and the prefetch unit prefetches the target information using the third information.

Abstract: A semiconductor device includes: a first cache that includes a first memory and rewrite flags that indicate whether rewriting has been performed for each piece of data held in the first memory; and a second cache that includes a second memory and a third memory that has a lower writing speed than the second memory, stores data evicted from the first cache in the second memory when a rewrite flag corresponding to the evicted data indicates a rewrite state, and stores data evicted from the first cache in the third memory when a rewrite flag corresponding to the evicted data indicates a non-rewrite state.

Abstract: An information processing apparatus includes: an arithmetic processing unit that includes: a processor that executes a program; and a cache memory coupled to the processor, wherein the cache memory includes: an acquisition unit that acquires a physical address of target information that is a target of an event that has occurred in the cache memory when the program is executed; and a generation unit that converts the physical address of the target information into a virtual address of the target information by using correspondence information that indicates correspondence between the physical address of the target information and the virtual address of the target information, and generates log information in which virtual address information that indicates the virtual address of the target information and identification information of the event are associated with each other.

Abstract: A device including: a processor executing a program; a first cache memory; a second cache memory belonging to a memory hierarchy lower than that of the first cache memory; a determination unit that determines, based on first information indicating a virtual address of information accessed in the second cache memory when the program is executed, second information indicating a virtual address of target information to be prefetched; and a prefetch unit that prefetches the target information and stores the prefetched target information in the second cache memory, wherein the second cache memory includes a conversion unit that converts, by using correspondence information indicating a correspondence relationship between the physical address of the target information and the virtual address of the target information, the second information into third information indicating a physical address of the target information, and the prefetch unit prefetches the target information using the third information.

Abstract: A wireless analysis device includes a memory configured to store information on a frequency spectrum of an incoming wave and information on a plurality of edges including a rising and falling edges of a signal included in the incoming wave, and a processor coupled to the memory and configured to compare a power change amount of the frequency spectrum at a first edge of the plurality of edges with a first threshold value for each frequency, specify a frequency range in which the power change amount is larger than the first threshold value, set a second threshold value based on a sum of the power change amount within the frequency range, and specify a second edge in which a sum of powers in the frequency range changes over the second threshold value among the plurality of edges, the second edge having different directions of power change from the first edge.

Abstract: There is provided a radio wave interference analysis apparatus configured to analyze a state of interference due to a plurality of interference signals of a plurality of interference sources on a target signal of a wireless device as an evaluation target at a reception point, the radio wave interference analysis apparatus including a memory, and a processor coupled to the memory and the processor configured to calculate a first probability of failure of reception of the target signal at the reception point due to collision of the target signal with an interference signal of the plurality of interference signals, calculate a second probability of failure of reception of the target signal at the reception point due to the interference signal of the plurality of interference sources, and output the first probability and the second probability.

Abstract: A wireless analysis device includes a memory configured to store information on a frequency spectrum of an incoming wave and information on a plurality of edges including a rising and falling edges of a signal included in the incoming wave, and a processor coupled to the memory and configured to compare a power change amount of the frequency spectrum at a first edge of the plurality of edges with a first threshold value for each frequency, specify a frequency range in which the power change amount is larger than the first threshold value, set a second threshold value based on a sum of the power change amount within the frequency range, and specify a second edge in which a sum of powers in the frequency range changes over the second threshold value among the plurality of edges, the second edge having different directions of power change from the first edge.

Abstract: There is provided a radio wave interference analysis apparatus configured to analyze a state of interference due to a plurality of interference signals of a plurality of interference sources on a target signal of a wireless device as an evaluation target at a reception point, the radio wave interference analysis apparatus including a memory, and a processor coupled to the memory and the processor configured to calculate a first probability of failure of reception of the target signal at the reception point due to collision of the target signal with an interference signal of the plurality of interference signals, calculate a second probability of failure of reception of the target signal at the reception point due to the interference signal of the plurality of interference sources, and output the first probability and the second probability.

Abstract: A power amplifier circuit includes unit amplifiers (unit PAs) whose output terminals are connected to one another, among which a number of unit PAs to be operated is controlled by an amplitude signal indicative of an amplitude of an input signal, and which output output signals based on a phase signal indicative of a phase of the input signal and an output current controller which controls an output current of each of the unit PAs. Each unit PA includes a first transistor and a second transistor connected in series between the output terminal and a ground. The first transistor receives the phase signal at a gate. The second transistor receives at a gate a control signal generated by the output current controller and determines the output current flowing to the output terminal on the basis of the control signal.

Abstract: A wireless communication apparatus configured to communicate with another wireless communication apparatus in a wireless network in accordance with a synchronized periods, includes a wireless communication device configured to send and receive a wireless signal with the other wireless communication apparatus, a memory, and a processor coupled to the memory and configured to acquire an index value related to a traffic amount within the wireless network, and determine, based on the index value, a first time length of a certain period during which the wireless communication device is in an ON state in a single period of the synchronized periods.

Abstract: A method of controlling wireless communication channels used in a plurality of wireless communication networks, the method includes performing, by a first wireless communication network, wireless communication using a first wireless channel, performing, by a second wireless communication network, wireless communication using of the first wireless channel, identifying a first value indicating a number of the wireless communication networks each of which performs wireless communication using the first wireless channel interfering with the wireless communication in the first wireless communication network, identifying a second value indicating a number of the wireless communication networks each of which performs wireless communication using the first wireless channel interfering with the wireless communication in the second wireless communication network, and switching, when the first value is greater than the second value the first wireless channel used by the first wireless communication network to a second w

Abstract: A power amplifier circuit includes unit amplifiers (unit PAs) whose output terminals are connected to one another, among which a number of unit PAs to be operated is controlled by an amplitude signal indicative of an amplitude of an input signal, and which output output signals based on a phase signal indicative of a phase of the input signal and an output current controller which controls an output current of each of the unit PAs. Each unit PA includes a first transistor and a second transistor connected in series between the output terminal and a ground. The first transistor receives the phase signal at a gate. The second transistor receives at a gate a control signal generated by the output current controller and determines the output current flowing to the output terminal on the basis of the control signal.

Abstract: A circuit design support apparatus includes a processor configured to calculate a time period necessary for a transition of a logical state, based on circuit configuration information indicating connection relations of elements of an integrated circuit and input information indicating a logical value input into an input terminal of the integrated circuit; calculate capacitance between power source wires in each logical state based on the circuit configuration information and the input information; and calculate temporal variation of the capacitance based on the capacitance and the time period.