Patents by Inventor Shihui Yin
Shihui Yin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11783875Abstract: In some embodiments, an in-memory-computing SRAM macro based on capacitive-coupling computing (C3) (which is referred to herein as “C3SRAM”) is provided. In some embodiments, a C3SRAM macro can support array-level fully parallel computation, multi-bit outputs, and configurable multi-bit inputs. The macro can include circuits embedded in bitcells and peripherals to perform hardware acceleration for neural networks with binarized weights and activations in some embodiments. In some embodiments, the macro utilizes analog-mixed-signal capacitive-coupling computing to evaluate the main computations of binary neural networks, binary-multiply-and-accumulate operations. Without needing to access the stored weights by individual row, the macro can assert all of its rows simultaneously and form an analog voltage at the read bitline node through capacitive voltage division, in some embodiments.Type: GrantFiled: May 31, 2022Date of Patent: October 10, 2023Assignee: The Trustees of Columbia University in the City of New YorkInventors: Mingoo Seok, Zhewei Jiang, Jae-sun Seo, Shihui Yin
-
Patent number: 11727261Abstract: A static random-access memory (SRAM) system includes SRAM cells configured to perform exclusive NOR operations between a stored binary weight value and a provided binary input value. In some embodiments, SRAM cells are configured to perform exclusive NOR operations between a stored binary weight value and a provided ternary input value. The SRAM cells are suitable for the efficient implementation of emerging deep neural network technologies such as binary neural networks and XNOR neural networks.Type: GrantFiled: November 4, 2021Date of Patent: August 15, 2023Assignees: Arizona Board of Regents on behalf of Arizona State University, The Trustees of Columbia University in the City of New YorkInventors: Jae-sun Seo, Shihui Yin, Zhewei Jiang, Mingoo Seok
-
Patent number: 11698952Abstract: A smart hardware security engine using biometric features and hardware-specific features is provided. The smart security engine can combine one or more entropy sources, including individually distinguishable biometric features, and hardware-specific features to perform secret key generation for user registration and authentication. Such hybrid signatures may be distinct from person-to-person (e.g., due to the biometric features) and from device-to-device (e.g., due to the hardware-specific features) while varying over time. Thus, embodiments described herein can be used for personal device authentication as well as secret random key generation, significantly reducing the scope of an attack.Type: GrantFiled: May 1, 2020Date of Patent: July 11, 2023Assignee: Arizona Board of Regents on behalf of Arizona State UniversityInventors: Jae-sun Seo, Shihui Yin, Sai Kiran Cherupally
-
Publication number: 20230089348Abstract: In some embodiments, an in-memory-computing SRAM macro based on capacitive-coupling computing (C3) (which is referred to herein as “C3SRAM”) is provided. In some embodiments, a C3SRAM macro can support array-level fully parallel computation, multi-bit outputs, and configurable multi-bit inputs. The macro can include circuits embedded in bitcells and peripherals to perform hardware acceleration for neural networks with binarized weights and activations in some embodiments. In some embodiments, the macro utilizes analog-mixed-signal capacitive-coupling computing to evaluate the main computations of binary neural networks, binary-multiply-and-accumulate operations. Without needing to access the stored weights by individual row, the macro can assert all of its rows simultaneously and form an analog voltage at the read bitline node through capacitive voltage division, in some embodiments.Type: ApplicationFiled: May 31, 2022Publication date: March 23, 2023Inventors: Mingoo Seok, Zhewei Jiang, Jae-sun Seo, Shihui Yin
-
Publication number: 20220318610Abstract: A programmable in-memory computing (IMC) accelerator for low-precision deep neural network inference, also referred to as PIMCA, is provided. Embodiments of the PIMCA integrate a large number of capacitive-coupling-based IMC static random-access memory (SRAM) macros and demonstrate large-scale integration of IMC SRAM macros. For example, a 28 nm prototype integrates 108 capacitive-coupling-based IMC SRAM macros of a total size of 3.4 megabytes (Mb), demonstrating one of the largest IMC hardware to date. In addition, a custom instruction set architecture (ISA) is developed featuring IMC and single-instruction-multiple-data (SIMD) functional units with hardware loop to support a range of deep neural network (DNN) layer types. The 28 nm prototype chip achieves a peak throughput of 4.9 tera operations per second (TOPS) and system-level peak energy-efficiency of 437 TOPS per watt (TOPS/W) at 40 megahertz (MHz) with a 1 volt (V) supply.Type: ApplicationFiled: April 4, 2022Publication date: October 6, 2022Inventors: Jae-sun Seo, Bo Zhang, Mingoo Seok, Shihui Yin
-
Publication number: 20220318628Abstract: Hardware noise-aware training for improving accuracy of in-memory computing (IMC)-based deep neural network (DNN) hardware is provided. DNNs have been very successful in large-scale recognition tasks, but they exhibit large computation and memory requirements. To address the memory bottleneck of digital DNN hardware accelerators, IMC designs have been presented to perform analog DNN computations inside the memory. Recent IMC designs have demonstrated high energy-efficiency, but this is achieved by trading off the noise margin, which can degrade the DNN inference accuracy. The present disclosure proposes hardware noise-aware DNN training to largely improve the DNN inference accuracy of IMC hardware. During DNN training, embodiments perform noise injection at the partial sum level, which matches with the crossbar structure of IMC hardware, and the injected noise data is directly based on measurements of actual IMC prototype chips.Type: ApplicationFiled: April 6, 2022Publication date: October 6, 2022Applicant: Arizona Board of Regents on behalf of Arizona State UniversityInventors: Sai Kiran Cherupally, Jian Meng, Shihui Yin, Deliang Fan, Jae?sun Seo
-
Publication number: 20220309330Abstract: A static random-access memory (SRAM) system includes SRAM cells configured to perform exclusive NOR operations between a stored binary weight value and a provided binary input value. In some embodiments, SRAM cells are configured to perform exclusive NOR operations between a stored binary weight value and a provided ternary input value. The SRAM cells are suitable for the efficient implementation of emerging deep neural network technologies such as binary neural networks and XNOR neural networks.Type: ApplicationFiled: November 4, 2021Publication date: September 29, 2022Inventors: Jae-sun Seo, Shihui Yin, Zhewei Jiang, Mingoo Seok
-
Patent number: 11355167Abstract: In some embodiments, an in-memory-computing SRAM macro based on capacitive-coupling computing (C3) (which is referred to herein as “C3SRAM”) is provided. In some embodiments, a C3SRAM macro can support array-level fully parallel computation, multi-bit outputs, and configurable multi-bit inputs. The macro can include circuits embedded in bitcells and peripherals to perform hardware acceleration for neural networks with binarized weights and activations in some embodiments. In some embodiments, the macro utilizes analog-mixed-signal capacitive-coupling computing to evaluate the main computations of binary neural networks, binary-multiply-and-accumulate operations. Without needing to access the stored weights by individual row, the macro can assert all of its rows simultaneously and form an analog voltage at the read bitline node through capacitive voltage division, in some embodiments.Type: GrantFiled: June 23, 2021Date of Patent: June 7, 2022Assignee: The Trustees of Columbia University in the City of New YorkInventors: Mingoo Seok, Zhewei Jiang, Jae-sun Seo, Shihui Yin
-
Patent number: 11170292Abstract: A static random-access memory (SRAM) system includes SRAM cells configured to perform exclusive NOR operations between a stored binary weight value and a provided binary input value. In some embodiments, SRAM cells are configured to perform exclusive NOR operations between a stored binary weight value and a provided ternary input value. The SRAM cells are suitable for the efficient implementation of emerging deep neural network technologies such as binary neural networks and XNOR neural networks.Type: GrantFiled: September 21, 2018Date of Patent: November 9, 2021Assignees: The Trustees of Columbia University in the City of New York, Arizona Board of Regents on Behalf of Arizona State UniversityInventors: Jae-sun Seo, Shihui Yin, Zhewei Jiang, Mingoo Seok
-
Publication number: 20210327474Abstract: In some embodiments, an in-memory-computing SRAM macro based on capacitive-coupling computing (C3) (which is referred to herein as “C3SRAM”) is provided. In some embodiments, a C3SRAM macro can support array-level fully parallel computation, multi-bit outputs, and configurable multi-bit inputs. The macro can include circuits embedded in bitcells and peripherals to perform hardware acceleration for neural networks with binarized weights and activations in some embodiments. In some embodiments, the macro utilizes analog-mixed-signal capacitive-coupling computing to evaluate the main computations of binary neural networks, binary-multiply-and-accumulate operations. Without needing to access the stored weights by individual row, the macro can assert all of its rows simultaneously and form an analog voltage at the read bitline node through capacitive voltage division, in some embodiments.Type: ApplicationFiled: June 23, 2021Publication date: October 21, 2021Inventors: Mingoo Seok, Zhewei Jiang, Jae-sun Seo, Shihui Yin
-
Patent number: 10827952Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for obtaining an electrocardiographic (ECG) signal of a user; obtaining a feature vector of the ECG signal of the user with neural network based feature extraction. Comparing the feature vector of the ECG signal with a stored feature vector of a registered user. Authenticating the user in response to determining that a similarity of the ECG feature vector of the ECG signal and the stored ECG feature vector of the registered user exceeds a pre-defined threshold value.Type: GrantFiled: April 28, 2017Date of Patent: November 10, 2020Assignee: Arizona Board of Regents on behalf of Arizona State UniversityInventors: Shihui Yin, Jae-sun Seo, Sang Joon Kim, Chisung Bae
-
Publication number: 20200349247Abstract: A smart hardware security engine using biometric features and hardware-specific features is provided. The smart security engine can combine one or more entropy sources, including individually distinguishable biometric features, and hardware-specific features to perform secret key generation for user registration and authentication. Such hybrid signatures may be distinct from person-to-person (e.g., due to the biometric features) and from device-to-device (e.g., due to the hardware-specific features) while varying over time. Thus, embodiments described herein can be used for personal device authentication as well as secret random key generation, significantly reducing the scope of an attack.Type: ApplicationFiled: May 1, 2020Publication date: November 5, 2020Applicant: Arizona Board of Regents on behalf of Arizona State UniversityInventors: Jae-sun Seo, Shihui Yin, Sai Kiran Cherupally
-
Publication number: 20190150794Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for obtaining an electrocardiographic (ECG) signal of a user; obtaining a feature vector of the ECG signal of the user with neural network based feature extraction. Comparing the feature vector of the ECG signal with a stored feature vector of a registered user. Authenticating the user in response to determining that a similarity of the ECG feature vector of the ECG signal and the stored ECG feature vector of the registered user exceeds a pre-defined threshold value.Type: ApplicationFiled: April 28, 2017Publication date: May 23, 2019Inventors: Sarma Vrudhula, Shihui Yin, Jae-sun Seo, Sang Joon Kim, Chisung Bae
-
Publication number: 20190087719Abstract: A static random-access memory (SRAM) system includes SRAM cells configured to perform exclusive NOR operations between a stored binary weight value and a provided binary input value. In some embodiments, SRAM cells are configured to perform exclusive NOR operations between a stored binary weight value and a provided ternary input value. The SRAM cells are suitable for the efficient implementation of emerging deep neural network technologies such as binary neural networks and XNOR neural networks.Type: ApplicationFiled: September 21, 2018Publication date: March 21, 2019Inventors: Jae-sun Seo, Shihui Yin, Zhewei Jiang, Mingoo Seok
-
Patent number: 9281476Abstract: Embodiments of the present invention disclose a resistive memory and a method for fabricating the same. The resistive memory comprises a bottom electrode, a resistive layer and a top electrode. The resistive layer is located over the bottom electrode. The top electrode is located over the resistive layer. A conductive protrusion is provided on the bottom electrode. The conductive protrusion is embedded in the resistive layer, and has a top width smaller than a bottom width. Embodiments of the present invention further disclose a method for fabricating a resistive memory. According to the resistive memory and the method for fabricating the same provided by the embodiments of the present invention, by means of providing the conductive protrusion on the bottom electrode, a “lightning rod” effect may be occurred so that an electric field in the resistive layer is intensively distributed near the conductive protrusion.Type: GrantFiled: July 8, 2013Date of Patent: March 8, 2016Assignee: Peking UniversityInventors: Yimao Cai, Shihui Yin, Ru Huang, Yichen Fang
-
Publication number: 20150144861Abstract: Embodiments of the present invention disclose a resistive memory and a method for fabricating the same. The resistive memory comprises a bottom electrode, a resistive layer and a top electrode. The resistive layer is located over the bottom electrode. The top electrode is located over the resistive layer. A conductive protrusion is provided on the bottom electrode. The conductive protrusion is embedded in the resistive layer, and has a top width smaller than a bottom width. Embodiments of the present invention further disclose a method for fabricating a resistive memory. According to the resistive memory and the method for fabricating the same provided by the embodiments of the present invention, by means of providing the conductive protrusion on the bottom electrode, a “lightning rod” effect may be occurred so that an electric field in the resistive layer is intensively distributed near the conductive protrusion.Type: ApplicationFiled: July 8, 2013Publication date: May 28, 2015Inventors: Yimao Cai, Shihui Yin, Ru Huang, Yichen Fang