Patents by Inventor Shijian Ge

Shijian Ge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250103544
    Abstract: Embodiments of the disclosure provide a method, an apparatus, a device, and a storage medium for resource configuration. The method includes obtaining an indication for the number of nodes of a NUMA node of a processor socket; dividing acceleration resources of an accelerator into at least one acceleration resource queue based on the number of nodes; and by associating the at least one acceleration resource queue to a respective NUMA node included in the processor socket, causing a plurality of processor cores divided into the respective NUMA node to use the at least one acceleration resource queue based on the association. Thus, the availability of the accelerator may be improved.
    Type: Application
    Filed: September 26, 2024
    Publication date: March 27, 2025
    Inventors: Qianjun XIE, Jingyi ZHANG, Xiangliang CHEN, Xiongshan AN, Shijian GE, Yongsu ZHANG, Yu ZHANG, Jian WANG
  • Publication number: 20250013474
    Abstract: The present disclosure relates to a terminal firmware startup method and apparatus, an electronic device, and a storage medium. The startup method includes: replacing a target feature program in initial firmware with a target loader to obtain target firmware; loading hardware code in the target firmware that is used for initializing core hardware to complete hardware initialization, and generating a hardware initialization complete instruction; loading the target loader according to the hardware initialization complete instruction to complete platform initialization, and generating an operating system startup signal; and starting an operating system.
    Type: Application
    Filed: November 18, 2022
    Publication date: January 9, 2025
    Inventors: Haitao NIE, Shijian GE, Xiaohan XU, Liang PENG, Yu ZHANG, Jian WANG
  • Publication number: 20240370272
    Abstract: The disclosure relates to a method, apparatus, computer-readable medium and electronic device for program loading. The method includes: loading the bin file at a program loading speed that is a first speed, adjusting the program loading speed to a second speed based on the configuration parameter in the bin file, the second speed being faster than the first speed, and then loading a FSBL at the program loading speed that is the second speed. By executing the configuration parameter in the bin file to adjust the speed of the Bootrom loading the FSBL from flash memory, the time for the Bootrom to load FSBL is shortened, and thus embedded systems are enabled to be compatible with various flash memories while also being applicable in occasions sensitive to startup time.
    Type: Application
    Filed: July 18, 2024
    Publication date: November 7, 2024
    Inventors: Zhenghao Gu, Shijian Ge, Xiang Shen, Xiaobo Yan, Jingjie Zhu, Bo Zhang, Yongsu Zhang, Yu Zhang, Jian Wang
  • Publication number: 20240370274
    Abstract: Embodiments of the present disclosure provide an operating system startup method, apparatus and electronic device. A specific implementation of the method comprises: determining at least one target mirror server from a mirror server cluster based on a LinuxBoot on a diskless server, wherein a mirror file stored in a mirror server comprises a system kernel and a file system; downloading mirror file fragments from a target mirror server of the at least one target mirror server based on the LinuxBoot; assembling a plurality of downloaded mirror file fragments into a target mirror file; and booting an operating system of the diskless server based on a target system kernel and a target file system comprised in the target mirror file. Therefore, the efficiency and success rate of diskless boot-up of an operating system of the diskless server can be improved when booting the operating system based on the LinuxBoot.
    Type: Application
    Filed: October 9, 2022
    Publication date: November 7, 2024
    Inventors: Zhenghao Gu, Shijian Ge, Yongji Xie, Lei Yu, Shuai Yuan, Xiaohan Xu, Xiaobo Yan, Yongsu Zhang, Yu Zhang, Jian Wang
  • Publication number: 20240256373
    Abstract: Embodiments of the present disclosure relate to a coprocessor, a host processor, a crash detection method and an electronic device. In this method, the coprocessor sends a handshake request to the host processor capable of running an operating system. The host processor performs an operation triggered by the handshake request. The host processor sends a positive response to the handshake request to the coprocessor if the operation is performed successfully; and the host processor sends, to the coprocessor, a negative response to the handshake request or no response if the operation is performed successfully. The coprocessor monitors a response to the handshake request from the host processor and determines a detection result of hardware crash associated with the operating system at least based on a monitoring result of this response.
    Type: Application
    Filed: January 19, 2024
    Publication date: August 1, 2024
    Inventors: Ligen YAN, Shijian GE, Zihao LV, Liang PENG, Yu ZHANG, Jian WANG, Haitao NIE, Chenchen LI
  • Patent number: 11894084
    Abstract: Method, systems and apparatuses may provide for technology that executes a margin test of a first memory storage based on a subset of first signals associated with the first memory storage. The technology determines, based on the margin test, first margin data to indicate whether the first memory storage complies with one or more electrical constraints. The technology determines, based on the first margin data, whether to execute a signal training process.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: February 6, 2024
    Assignee: Intel Corporation
    Inventors: Dujian Wu, Shijian Ge, Daocheng Bu
  • Publication number: 20220093197
    Abstract: Method, systems and apparatuses may provide for technology that executes a margin test of a first memory storage based on a subset of first signals associated with the first memory storage. The technology determines, based on the margin test, first margin data to indicate whether the first memory storage complies with one or more electrical constraints. The technology determines, based on the first margin data, whether to execute a signal training process.
    Type: Application
    Filed: February 8, 2019
    Publication date: March 24, 2022
    Applicant: Intel Corporation
    Inventors: Dujian WU, Shijian GE, Daocheng BU
  • Publication number: 20210311818
    Abstract: Systems, apparatuses and methods may provide for technology that handles failures in memory hardware (e.g., dynamic random access memory (DRAM)) via runtime post package repair. Such technology may include operations to perform a runtime post package repair in response to a memory hardware failure detected in the memory. In such an example, the runtime post package repair may be done after power up boot operations have been completed.
    Type: Application
    Filed: December 11, 2018
    Publication date: October 7, 2021
    Applicant: INTEL CORPORATION
    Inventors: Vincent Zimmer, Anil Agrawal, Dujian Wu, Shijian Ge, Zhenglong Wu