Abstract: A multi-level cell thin-film transistor memory and a method of fabricating the same, a structure of which memory comprises sequentially from down to top: a gate electrode, a charge blocking layer, a charge trapping layer, a charge tunneling layer, an active region, and source and drain electrodes; wherein the charge tunneling layer fully encloses the charge trapping layer so as to completely isolate the charge trapping layer from the ambience, which prevents change of physical properties and chemical compositions of the charge trapping layer during the annealing treatment, reduces loss of charges stored in the charge trapping layer, and enhances data retention property and device performance stability; a metal oxide semiconductor thin film is utilized as the charge trapping layer of the memory, which implements multi-level cell storage and improves storage density.

Abstract: A multi-level cell thin-film transistor memory and a method of fabricating the same, a structure of which memory comprises sequentially from down to top: a gate electrode, a charge blocking layer, a charge trapping layer, a charge tunneling layer, an active region, and source and drain electrodes; wherein- the charge tunneling layer fully encloses the charge trapping layer so as to completely isolate the charge trapping layer from the ambience, which prevents change of physical properties and chemical compositions of the charge trapping layer during the annealing treatment, reduces loss of charges stored in the charge trapping layer, and enhances data retention property and device performance stability; a metal oxide semiconductor thin film is utilized as the charge trapping layer of the memory, which implements multi-level cell storage and improves storage density

Abstract: A method and corresponding reactor for depositing metal-nitride thin film with adjustable metal contents. The method includes several first and second half reaction process. By adjusting the ratio of first and second half reaction cycles, metal nitride thin films with different metal contents can be grown. The first half reaction process is the decomposition of metal-organic precursor adsorbed on the substrate surface, leaving behind metal atom layer by light irradiation. The second half reaction process forms metal nitride thin films by the reaction of NH3 plasma and the metal atomic layer on the substrate surface. This method can control the ratio between metal and nitrogen atom content in the film, thus achieving the regulation of film resistivity. In addition, this method offers favorable film step coverage and accurate film thickness control capability, which is significantly applicable for the film meeting the requirement of advanced CMOS integrated circuit technology.

Abstract: A method and corresponding reactor for depositing metal-nitride thin film with adjustable metal contents. The method includes several first and second half reaction process. By adjusting the ratio of first and second half reaction cycles, metal nitride thin films with different metal contents can be grown. The first half reaction process is the decomposition of metal-organic precursor adsorbed on the substrate surface, leaving behind metal atom layer by light irradiation. The second half reaction process forms metal nitride thin films by the reaction of NH3 plasma and the metal atomic layer on the substrate surface. This method can control the ratio between metal and nitrogen atom content in the film, thus achieving the regulation of film resistivity. In addition, this method offers favorable film step coverage and accurate film thickness control capability, which is significantly applicable for the film meeting the requirement of advanced CMOS integrated circuit technology.

Abstract: A semiconductor memory device with a buried drain is provided. The device comprises a semiconductor substrate (107); one drain region (108) of a first doping type; two source regions (101a, 101b) of a second doping type; and a stacked gate provided on the semiconductor substrate for capturing electrons. A memory array formed by a plurality of semiconductor memory devices and a manufacturing method thereof are also provided. The semiconductor memory device has the advantages of small cell area, simple manufacturing process and the like. The manufacturing cost of the memory device is reduced and the storing density of the memory device is increased.

Abstract: The invention relates to a thin film transistor memory and its fabricating method. This memory using the substrate as the gate electrode from bottom to up includes a charge blocking layer, a charge storage layer, a charge tunneling layer, an active region of the device and source/drain electrodes. The charge blocking layer is the ALD grown Al2O3 film. The charge storage layer is the two layer metal nanocrystals which include the first layer metal nanocrystals, the insulating layer and the second layer metal nanocrystals grown by ALD method in sequence from bottom to up. The charge tunneling layer is the symmetrical stack layer which includes the SiO2/HfO2/SiO2 or Al2O3/HfO2/Al2O3 film grown by ALD method in sequence from bottom to up. The active region of the device is the IGZO film grown by the RF sputtering method, and it is formed by the standard lithography and wet etch method.

Abstract: The invention relates to a thin film transistor memory and its fabricating method, This memory using the substrate as the gate electrode from bottom to up includes a charge blocking layer, a charge storage layer, a charge tunneling layer, an active region of the device and source/drain electrodes. The charge blocking layer is the ALD grown Al2O3 film. The charge storage layer is the two layer metal nanocrystals which include the first layer metal nanocrystals, the insulting layer and the second layer metal nanocrystals grown by ALD method. in sequence from bottom to up. The charge tunneling layer is the symmetrical stack layer which includes the SiO2/HfO2/SiO2 or Al2O3/HfO2/Al2O3 film grown. by ALD method in sequence from bottom to up. The active region of the device is the IGZO film grown by the RF sputtering method, and it is formed by the standard lithography and wet etch method.

Abstract: The invention relates to a gate stack structure suitable for use in a semiconductor flash memory device and its fabricating method. The gate stack structure is fabricated on a p-type 100 silicon substrate, which also includes the following components in sequence from bottom to top: a charge tunnel layer of Al2O3 film, the first charge trapping layer of RuOx nanocrystals; the second charge trapping layer of high-k HxAlyOz film, a charge blocking layer of Al2O3 film, and a top electrode. In this invention, the RuOx nanocrystals have excellent thermal stability, and do not diffuse easily at high temperatures. The high-k HfxAlyOz film has high density charge traps.Pd with a high work function is used as the top electrode. Therefore, the present gate stack structure has vast practical prospects for nanocrystal memory devices.

Abstract: A method of silicon wafer alignment used in through-silicon-via interconnection for use in the field of high-integrity packaging technology is disclosed. In one aspect, the method includes aligning and calibrating the upper and lower silicon wafers, stacked and interconnected electrically, so as to improve alignment accuracy of silicon wafers and reduce interconnection resistances. In some embodiments, the integrated circuit chip made by the method improves speed and energy performance.

Abstract: A semiconductor memory device with a buried drain is provided. The device comprises a semiconductor substrate (107); one drain region (108) of a first doping type; two source regions (101a,101b) of a second doping type; and a stacked gate provided on the semiconductor substrate for capturing electrons. A memory array formed by a plurality of semiconductor memory devices. and a manufacturing method thereof are also provided. The semiconductor memory device has the advantages of small cell area, simple manufacturing process and the like. The manufacturing cost of the memory device is reduced and the storing density of the memory device is increased.

Abstract: The present invention refers to a semiconductor device especially a tunneling filed effect transistor (TFET) using narrow bandgap material as the source electrode material. A Semiconductor device which is a tunneling field effect transistor type semiconductor device, in which the source material is characterized as narrow band-gap material; meanwhile, there is a u-groove channel. The narrow band-gap material results in a raise of driving current and the u-groove channel reduced drain leakage current. The TFET disclosed in to present invention has the advantages of low leakage current, high drive current, and high integration density. The static power consumption is also reduced by using the present invention. The integration density is improved as well.

Abstract: The present invention belongs to the technical field of semiconductor devices, and discloses a power device using photoelectron injection to modulate conductivity and the method thereof. The power device comprises at least one photoelectron injection light source and a power MOS transistor. The present invention uses photoelectron injection method to inject carriers to the drift region under the gate of the power MOS transistor, thus modulating the conductivity and further decreasing the specific on-resistance of the power MOS transistor. Moreover, as the doping concentration of the drift region can be decreased and the blocking voltage can be increased, the performance of the power MOS transistor can be greatly improved and the application of power MOS transistor can be expanded to high-voltage fields.