Abstract: The invention provides a CMOS GOA circuit, which improves the NAND gate in the latch module and the inverter to connect the latch clock signal to the NAND gate in the latch module or the inverter to control the latch module to realize the input and latch of the cascade signal through the voltage change in the latch clock signal. Compared to the known technique, the present invention reduces the number of TFTs required by the latch module without affecting the normal operation of the circuit, and facilitates the implementation of the narrow border or borderless display products.

Abstract: A driving method for a pixel circuit comprises steps of: receiving a data control signal inputted by a driving chip and resetting a data line of a pixel unit according to the data control signal; charging the pixel unit to a target voltage according to the data line control signal; and receiving a control signal to control the pixel unit to display a corresponding grayscale level according to the target voltage. Through above way, the present invention can prevent a wrong charging which will generate an abnormal picture display.

Abstract: The present disclosure relates to an organic diode display driving circuit, a display panel, and an electronic device. The driving circuit includes a voltage source, a display-area circuit, and an auxiliary-area circuit being arranged outside a display area. The display-area circuit and the auxiliary-area circuit include power-supply wirings, signal wirings, and at least one pixel, and the voltage source connects to the pixel within the display area via the power-supply wirings. The voltage source further directly or indirectly connects to the pixel within the display area via the wirings in an auxiliary area. By configuring the wirings in the auxiliary area to connect to the voltage line, the resistance of the power-supply wirings in the display area may be reduced so as to eliminate the voltage drop of the power-supply wirings in the display area.

Abstract: The CMOS GOA circuit of reducing clock signal loading comprises the input control module (1), the latch module (2), the reset module (3), the signal process module (4) and the output buffer module (5); in the input control module (1), the clock signal (CK(M)) merely needs to control the second N type thin film transistor and the fifth N type thin film transistor (T2, T5), and the amount of the thin film transistors driven by the clock signal can be decreased to reduce the clock signal loading, and to lower the RC delay and the power consumption of the clock signal; the latch module (2) utilizes the inverted scan drive signal (XGate(N?2)) of the two former N-2th stage GOA unit to be the input control signal of the stage transfer signal Q(N) to solve the competition problem occurs as the stage transfer signal (Q(N)) is inputted.

Abstract: The CMOS GOA circuit of reducing clock signal loading comprises the input control module (1), the latch module (2), the reset module (3), the signal process module (4) and the output buffer module (5); in the input control module (1), the clock signal (CK(M)) merely needs to control the second N type thin film transistor and the fifth N type thin film transistor (T2, T5), and the amount of the thin film transistors driven by the clock signal can be decreased to reduce the clock signal loading, and to lower the RC delay and the power consumption of the clock signal; the latch module (2) utilizes the inverted scan drive signal (XGate(N?2)) of the two former N-2th stage GOA unit to be the input control signal of the stage transfer signal Q(N) to solve the competition problem occurs as the stage transfer signal (Q(N)) is inputted.

Abstract: The present invention provides a liquid crystal display panel. The array test circuit (200) comprises a test control unit including a N type thin film transistor and a P type thin film transistor, wherein one thin film transistor is employed to be the output thin film transistor, and the other thin film transistor is employed to be the voltage stabilization thin film transistor. When the liquid crystal display panel is in the normal display state, the test control signal (ATEN) controls the output thin film transistor to be deactivated and controls the voltage stabilization thin film transistor to be activated so that the voltage difference of the gate and the source of the output thin film transistor is zero. Thus, the leakages on the data lines in the active display area (100) are consistent.

Abstract: The present invention provides a liquid crystal display panel. The array test circuit (200) comprises a test control unit including a N type thin film transistor and a P type thin film transistor, wherein one thin film transistor is employed to be the output thin film transistor, and the other thin film transistor is employed to be the voltage stabilization thin film transistor. When the liquid crystal display panel is in the normal display state, the test control signal (ATEN) controls the output thin film transistor to be deactivated and controls the voltage stabilization thin film transistor to be activated so that the voltage difference of the gate and the source of the output thin film transistor is zero. Thus, the leakages on the data lines in the active display area (100) are consistent.

Abstract: A scan driving circuit is provided. The scan driving circuit for driving cascaded scan lines includes a scan driving circuit, a latch module, a driving-signal generation module, an output control module, a high gate voltage source, and a low level gate voltage. The scan driving circuit of the present invention conducts a driving operation for the latch module by a first cascade signal and a second cascade signal, so that a clock signal is not required to be processed with a phase inversion, and thereby the scan driving circuit has less overall power consumption.

Abstract: A display panel and thin film transistor array substrate are provided. The thin film transistor array substrate includes an active area and a peripheral region. The thin film transistor array substrate further includes a base substrate, a light shield metal layer, a first insulating layer, a semiconductor layer, a second insulating layer, a first signal line layer, a second signal line layer, a third signal line layer, a third insulating layer, a fourth insulating layer, a common line layer, a fifth insulating layer, and a pixel electrode layer. The present invention prevents display failure problems caused by the signal line being disconnected.

Abstract: A scan driving circuit is provided. The scan driving circuit for driving cascaded scan lines includes a scan driving circuit, a latch module, a driving-signal generation module, an output control module, a high gate voltage source, and a low level gate voltage. The scan driving circuit of the present invention conducts a driving operation for the latch module by a first cascade signal and a second cascade signal, so that a clock signal is not required to be processed with a phase inversion, and thereby the scan driving circuit has less overall power consumption.