Patents by Inventor Shijun Liang

Shijun Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240136461
    Abstract: A retinomorphic sensor array and a convolution method are used for image processing therefor, wherein the optoelectronic sensor has a vertically stacked heterostructure provided with a bottom electrode, a dielectric layer, a channel layer, a source electrode and a drain electrode on a base, the source and drain electrode are mutually opposite and are arranged at two ends of the channel layer, the bottom electrode, the source and drain electrode are made of a material used by a flexible electrode, an inert metal or a semimetal, the dielectric layer is made of an insulating material, the channel layer is made of a bipolar material, and the base comprises a substrate and an insulating material layer generated on a surface of the substrate.
    Type: Application
    Filed: March 25, 2020
    Publication date: April 25, 2024
    Inventors: Feng MIAO, Shijun LIANG, Chenyu WANG
  • Publication number: 20240054177
    Abstract: A device for parallelizing analog in-memory computing based on frequency division multiplexing comprises an input circuit, a memory array and an output circuit, wherein an input of the memory array is connected with an output of the input circuit, and an output of the memory array is connected with an input of the output circuit; the input circuit modulates k data in each row of m×k input data matrix into each path of frequency division multiplexing signals for output by using k different frequency sources; the memory array comprises m×n memory elements, memory weights thereof form an m×n matrix, and m×1 input frequency division multiplexing signals are parallel-processed in the memory array; and the output circuit demodulates and separates each path of frequency division multiplexing signals output by the memory array into k data.
    Type: Application
    Filed: May 31, 2021
    Publication date: February 15, 2024
    Inventors: Feng MIAO, Shijun LIANG, Cong WANG
  • Publication number: 20230196084
    Abstract: A tunable homojunction field effect device-based artificial synapse circuit includes a first tunable homojunction field effect device M1, a second tunable homojunction field effect device M2, a third tunable homojunction field effect device M3, and a capacitor C; the tunable homojunction field effect device can exhibit the electrical properties of NN junction, PP junction, PN junction, and NP junction under the control of gate voltage; in the circuit, whether the device M2 and the device M3 are turned on rely on the combined action of presynaptic pulse and postsynaptic pulse; compared with the circuit structure of a traditional CMOS circuit scheme which exhibits neural synaptic functions of spike-time-dependent plasticity and continuously adjustable pulse-to-synaptic weight, the circuit in the present solution requires a greatly reduced number of devices and shows the feature of reconfigurable function, exhibiting a great advantage in constructing low-power, high-density integrated bionic chips for future neu
    Type: Application
    Filed: July 2, 2020
    Publication date: June 22, 2023
    Inventors: Feng MIAO, Shijun LIANG, Chen PAN, Chenyu WANG, Pengfei WANG
  • Publication number: 20230198520
    Abstract: A tunable homojunction field effect device-based unit circuit and a multifunctional logic circuit, and the corresponding design scheme includes four steps: a structural construction of the tunable homojunction device, an implementation of multi-functional electrical operations of the tunable homojunction device, a design of a basic logic unit circuit, and an implementation of complex logic functions by a cascaded unit logic circuit; the first designs a tunable homojunction device based on a material with bipolar field effect characteristics; and then introduces the polarity of source-drain voltage into the device as an additional control signal; further, by cascading three reconfigurable logic units, the multi-functional logic circuit that can perform logic functions of full adder and subtractor is designed; the logic unit circuit designed in the present invention has the ability to perform reconfigurable logic functions.
    Type: Application
    Filed: July 2, 2020
    Publication date: June 22, 2023
    Inventors: Feng MIAO, Shijun LIANG, Chen PAN
  • Publication number: 20230186060
    Abstract: A retinomorphic array is used to convert visual information into electrical signals, and the neural network performs information processing on the input electrical signals to obtain the result of visual cognition; the perception and synchronous preprocessing of visual information is achieved through the retinomorphic array, avoiding the transmission of a large number of redundant visual information from the photoreceptor end to the image information processor, saving bandwidth resources, and improving the efficiency of visual information processing; the use of the crossbar array allows the configuration of a neural network with a more complex structure and more diverse functions, and the higher-level processing of visual information by the neural network realizes a novel neuromorphic vision system integrated therein with image recognition, dynamic tracking, and trajectory prediction.
    Type: Application
    Filed: August 28, 2020
    Publication date: June 15, 2023
    Inventors: Feng MIAO, Shijun LIANG, Shuang WANG
  • Publication number: 20220331952
    Abstract: A system and a method for robot control based on a memristive crossbar array comprises a sensor group, an input sensing signal modulator, a neuromorphic circuit, an output control signal modulator, an output device, an external supervisor module and a training controller; the neuromorphic circuit performs robot control, and the main part thereof is a memristor crossbar array with a fully-connected neural network structure, wherein a differential amplifying circuit and a multiplexing switch in the neuromorphic circuit are connected to the memristor crossbar array, an input signal vector is multiplied by a weight matrix stored in the memristor crossbar array, and one or more channels of analog output signals are obtained through the differential amplifying circuit.
    Type: Application
    Filed: November 1, 2019
    Publication date: October 20, 2022
    Inventors: Feng MIAO, Shijun LIANG, Cong WANG, Zaizheng YANG
  • Patent number: D934021
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: October 26, 2021
    Assignee: SHENZHEN VANTOP TECHNOLOGY & INNOVATION CO., LTD.
    Inventors: Zhuocheng Luo, Shijun Liang