Patents by Inventor Shikayuki Ochi

Shikayuki Ochi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4599576
    Abstract: An insulated gate type field effect transistor for high power which has a low conductivity region surrounding a drain region and an offset gate region having a further lower conductivity adjoined thereto, wherein the length and impurity concentration are designed according to the electric characteristics of the transistor. A combination of P channel and N channel type transistors having substantially the same electric characteristics and an audio amplifying circuit using the combination are also disclosed.
    Type: Grant
    Filed: March 1, 1978
    Date of Patent: July 8, 1986
    Assignee: Hitachi, Ltd.
    Inventors: Isao Yoshida, Takeaki Okabe, Shikayuki Ochi, Hidefumi Ito, Masatomo Furumi, Masaru Takeuchi, Minoru Nagata
  • Patent number: 4443812
    Abstract: A high-breakdown-voltage semiconductor device wherein a resistor body made of a P-type impurity region is disposed in a surface region of an N-type semiconductor body so as to form a resistor element, a P-type low doped region is disposed around the resistor body, and a plate layer which extends from a high potential electrode of the resistor body covers a main part of the P-type low doped region.
    Type: Grant
    Filed: February 4, 1981
    Date of Patent: April 17, 1984
    Assignee: Hitachi, Ltd.
    Inventors: Ichiro Imaizumi, Masatoshi Kimura, Shikayuki Ochi, Masayoshi Yoshimura, Takashi Yamaguchi, Toyomasa Koda
  • Patent number: 4423433
    Abstract: A high-breakdown-voltage resistance element comprises a semiconductor body, an impurity layer disposed in a surface region of the semiconductor body to provide a resistor body, a first electrode connected to one end of the resistor body through a contact hole in a first insulating film formed on the surface of the semiconductor body, and a second electrode connected to the other end of the resistor body through another contact hole in the insulating film. A second insulating film is formed on the first and second electrodes, and a third electrode is connected to the first electrode through a contact hole in the second insulating film, so that the entire surface of the resistor body and adjacent areas are covered with the first, second and third electrodes.
    Type: Grant
    Filed: June 3, 1980
    Date of Patent: December 27, 1983
    Assignee: Hitachi, Ltd.
    Inventors: Ichiro Imaizumi, Shikayuki Ochi, Masatoshi Kimura, Masayoshi Yoshimura, Takashi Yamaguchi, Toyomasa Koda
  • Patent number: 4317055
    Abstract: A high-voltage circuit for insulated gate field-effect transistors (MOSFETs) is provided wherein two MOSFETs are connected in series, the source and gate of the first MOSFET being respectively used as a source terminal and gate terminal of the high-voltage circuit, the drain of the second MOSFET being used as a drain terminal of the circuit. First and second resistors are connected in series between the source terminal and the drain terminal, and a biasing voltage supply is connected between the juncture of both the resistors and the gate of the second MOSFET. By virtue of these connections the "on" resistance of the high-voltage circuit is improved due to the effect of the biasing voltage effect in bringing the second MOSFET into an "on" condition.
    Type: Grant
    Filed: May 8, 1979
    Date of Patent: February 23, 1982
    Assignee: Hitachi, Ltd.
    Inventors: Isao Yoshida, Minoru Nagata, Shikayuki Ochi, Hisao Katto
  • Patent number: 4213140
    Abstract: An insulated-gate semiconductor device wherein a first region is formed in the surface of a semiconductor substrate, the first region having a conductivity type opposite to that of the substrate, two insulated-gate FET's are formed within the first region, the drain of the first insulated-gate FET and that of the second insulated-gate FET are made common, the drains are electrically connected to the first region, and the gate of the first insulated-gate FET and the source of the second insulated-gate FET, and the gate of the second insulated-gate FET and the source of the first insulated-gate FET are respectively connected, thereby to prevent the occurrence of a negative resistance.
    Type: Grant
    Filed: July 6, 1978
    Date of Patent: July 15, 1980
    Assignee: Hitachi, Ltd.
    Inventors: Takeaki Okabe, Isao Yoshida, Mineo Katsueda, Hidefumi Ito, Masatomo Furumi, Shikayuki Ochi
  • Patent number: 4172260
    Abstract: In an insulated gate field effect transistor having a source region and a drain region of the P-conductivity type which are disposed in surface portions of a semiconductor substrate of the N-conductivity type in a manner to be spaced apart from each other, a gate electrode being disposed through an insulating film on the substrate between the source region and the drain region, an insulated gate field effect transistor wherein said drain region is disposed apart from said gate electrode, two regions of an intermediate region and a high resistance region which are of the P-conductivity type and which successively extend from said drain region towards the side of said gate electrode are disposed in surface portions of the substrate situated between said drain region and said gate electrode, said intermediate region having an impurity concentration lower than that of said drain region, said high resistance region having an impurity concentration lower than that of said intermediate region, and a source electrode
    Type: Grant
    Filed: November 21, 1977
    Date of Patent: October 23, 1979
    Assignee: Hitachi, Ltd.
    Inventors: Takeaki Okabe, Isao Yoshida, Shikayuki Ochi, Hidefumi Itoh, Masatomo Furumi, Toru Toyabe, Mineo Katsueda, Yukio Shirota