Abstract: The signal toggling detection and correction circuit includes a flip-flop, a checker circuit, and a fault monitoring circuit that includes a restoration circuit. Based on faults such as soft errors and unintended bit toggles in the flip-flop, a flop output signal toggles. A set of checker signals outputted by the checker circuit may toggle based on toggling of the flop output signal and a restoration signal of the restoration circuit. Based on the toggling of at least one checker signal, the fault monitoring circuit determines whether the flip-flop or the checker circuit is faulty. When the checker circuit is faulty, the fault monitoring circuit corrects the toggling of at least one checker signal. When the flip-flop is faulty, the fault monitoring circuit corrects the toggling of one of the toggled flop output signal or the restoration signal and further corrects the toggled checker signal.

Abstract: The signal toggling detection and correction circuit includes a flip-flop, a checker circuit, and a fault monitoring circuit that includes a restoration circuit. Based on faults such as soft errors and unintended bit toggles in the flip-flop, a flop output signal toggles. A set of checker signals outputted by the checker circuit may toggle based on toggling of the flop output signal and a restoration signal of the restoration circuit. Based on the toggling of at least one checker signal, the fault monitoring circuit determines whether the flip-flop or the checker circuit is faulty. When the checker circuit is faulty, the fault monitoring circuit corrects the toggling of at least one checker signal. When the flip-flop is faulty, the fault monitoring circuit corrects the toggling of one of the toggled flop output signal or the restoration signal and further corrects the toggled checker signal.

Abstract: A scan flip-flop includes a selection circuit, a primary latch, a secondary latch, and a data retention latch. The selection circuit selects and outputs one of functional data, first reference data, scan data, and first control data as second reference data. The primary latch receives the second reference data and outputs third reference data, whereas the secondary latch receives the third reference data and outputs second control data. The second control data is then provided to a subsequent scan flip-flop of a scan chain. The data retention latch receives one of the third reference data and the second control data, and outputs and provides the first reference data to the selection circuit. The first reference data corresponds to functional data retained in the scan flip-flop during a structural testing mode associated with the scan chain.

Abstract: An integrated circuit (IC) has scan chains of stitched registers that support scan testing of functional logic. The scan testing has a shift phase in which incoming and outgoing data are shifted into and out of the registers using a slow clock and a capture phase in which outgoing data from the functional logic is captured by the registers using launch-and-capture pulses of a fast clock to check for delay faults. During a warm-up period after termination of the slow clock but before application of the launch-and-capture pulses, the registers propagate data through their master latches without affecting the data stored in their slave latches. A warm-up controller configures the registers and generates control signals to perform either launch-on-shift or launch-on-capture scan testing. The flow of data and the warm-up controller operations keep the power supply rail voltage sufficiently charged for the fast launch-and-capture pulses.

Abstract: An integrated circuit (IC) has scan chains of stitched registers that support scan testing of functional logic. The scan testing has a shift phase in which incoming and outgoing data are shifted into and out of the registers using a slow clock and a capture phase in which outgoing data from the functional logic is captured by the registers using launch-and-capture pulses of a fast clock to check for delay faults. During a warm-up period after termination of the slow clock but before application of the launch-and-capture pulses, the registers propagate data through their master latches without affecting the data stored in their slave latches. A warm-up controller configures the registers and generates control signals to perform either launch-on-shift or launch-on-capture scan testing. The flow of data and the warm-up controller operations keep the power supply rail voltage sufficiently charged for the fast launch-and-capture pulses.