Abstract: The present disclosure provides a storage array, and an interconnection structure and a method for operating thereof. The storage array includes: storage units and transistors located in each column and each row, each transistor having a first source/drain and a second source/drain; wherein, a storage unit in an odd-numbered column connected to a first bit line and a second source line; the first source/drain of a transistor in an odd-numbered column is connected to a first source line; the second source/drain of a transistor in an odd-numbered column is connected to a second source line; a storage unit in an even-numbered column connected to a second bit line and a first source line; the first source/drain of a transistor in an even-numbered column is connected to a second source line; and the second source/drain of a transistor in an even-numbered column is connected to a first source line.

Abstract: Disclosed in the present application are a memory and a method for manufacturing thereof. The manufacturing method includes: bottom electrodes of a memory array region and a first portion of top contact body of a logic region are formed on an upper surface of a bottom circuit layer simultaneously; a patterned dielectric layer is formed on an upper surface of a memory cell layer in the memory array region and the logic region; hard masks and a second portion of top contact body are formed in a via of the patterned dielectric layer simultaneously, where the hard masks corresponds to the bottom electrodes, and the second portion of top contact body is connected to the first portion of top contact body in a contact manner; and the memory cell layer is etched to form memory cells.

Abstract: The present disclosure provides a storage array, and an interconnection structure and a method for operating thereof. The storage array includes: storage units and transistors located in each column and each row, each transistor having a first source/drain and a second source/drain; wherein, a storage unit in an odd-numbered column has one end connected to a first bit line and a second source line; the first source/drain of a transistor in an odd-numbered column is connected to a first source line; the second source/drain of a transistor in an odd-numbered column is connected to a second source line; a storage unit in an even-numbered column connected to a second bit line and a first source line; the first source/drain of a transistor in an even-numbered column is connected to a second source line; and the second source/drain of a transistor in an even-numbered column is connected to a first source line.

Abstract: The present invention relates to methods for inhibiting or preventing ocular processes associated with CTGF. Methods and agents for use in treating or preventing ocular disorders, methods for diagnosing ocular disorders and related kits, and methods for screening for agents for use in the present methods are also provided.