Patents by Inventor Shiliang Hu
Shiliang Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11755099Abstract: Example methods and apparatus to facilitate dynamic core selection are disclosed. An example apparatus includes a first processor core of a first type; a second processor core of a second type different from the first type; and software to: access a user-supplied hint indicative of a user preference to execute program code on the first processor core, the user-supplied hint including a user-defined attribute of the program code; monitor performance of the program code on the first processor core; determine, based on the user-defined attribute of the program code, a predicted performance of the program code on the second processor core is better than the performance of the program code on the first processor core; and ignore the user preference by migrating the program code from the first processor core for execution on the second processor core.Type: GrantFiled: June 28, 2022Date of Patent: September 12, 2023Assignee: Intel CorporationInventors: Youfeng Wu, Shiliang Hu, Edson Borin, Cheng Wang
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Publication number: 20220326756Abstract: Example methods and apparatus to facilitate dynamic core selection are disclosed.Type: ApplicationFiled: June 28, 2022Publication date: October 13, 2022Inventors: Youfeng Wu, Shiliang Hu, Edson Borin, Cheng Wang
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Patent number: 10534424Abstract: Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.Type: GrantFiled: January 2, 2016Date of Patent: January 14, 2020Assignee: Intel CorporationInventors: Youfeng Wu, Shiliang Hu, Edson Borin, Cheng Wang
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Patent number: 10474471Abstract: One or more embodiments may provide a method for performing a replay. The method includes initiating execution of a program, the program having a plurality of sets of instructions, and each set of instructions has a number of chunks of instructions. The method also includes intercepting, by a virtual machine unit executing on a processor, an instruction of a chunk of the number of chunks before execution. The method further includes determining, by a replay module executing on the processor, whether the chunk is an active chunk, and responsive to the chunk being the active chunk, executing the instruction.Type: GrantFiled: April 18, 2016Date of Patent: November 12, 2019Assignee: Intel CorporationInventors: Justin E. Gottschlich, Klaus Danne, Cristiano L. Pereira, Gilles A. Pokam, Rolf Kassa, Shiliang Hu, Tim Kranich
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Publication number: 20190332158Abstract: Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.Type: ApplicationFiled: July 11, 2019Publication date: October 31, 2019Inventors: Youfeng Wu, Shiliang Hu, Edson Borin, Cheng Wang
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Patent number: 10437318Abstract: Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.Type: GrantFiled: January 2, 2016Date of Patent: October 8, 2019Assignee: Intel CorporationInventors: Youfeng Wu, Shiliang Hu, Edson Borin, Cheng Wang
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Patent number: 10437319Abstract: Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.Type: GrantFiled: January 2, 2016Date of Patent: October 8, 2019Assignee: Intel CorporationInventors: Youfeng Wu, Shiliang Hu, Edson Borin, Cheng Wang
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Patent number: 10394561Abstract: A mechanism is described for facilitating dynamic and efficient management of instruction atomicity violations in software programs according to one embodiment. A method of embodiments, as described herein, includes receiving, at a replay logic from a recording system, a recording of a first software thread running a first macro instruction, and a second software thread running a second macro instruction. The first software thread and the second software thread are executed by a first core and a second core, respectively, of a processor at a computing device. The recording system may record interleavings between the first and second macro instructions. The method includes correctly replaying the recording of the interleavings of the first and second macro instructions precisely as they occurred. The correctly replaying may include replaying a local memory state of the first and second macro instructions and a global memory state of the first and second software threads.Type: GrantFiled: October 19, 2016Date of Patent: August 27, 2019Assignee: INTEL CORPORATIONInventors: Nathan D. Dautenhahn, Justin Gottschlich, Gilles Pokam, Cristiano Pereira, Shiliang Hu, Klaus Danne, Rolf Kassa
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Patent number: 10387296Abstract: Methods and systems to identify threads responsible for causing a concurrency bug in a computer program having a plurality of concurrently executing threads are disclosed. An example method disclosed herein includes defining, with a processor, a data type. The data type including a first predicate, the first predicate being invoked using a first program instruction inserted in a first thread of the plurality of threads, a second predicate, the second predicate being invoked using a second program instruction inserted in a second thread of the plurality of threads, and an expression defining a relationship between the first predicate and the second predicate. The method further includes, in response to determining the relationship is satisfied during execution of the computer program, identifying the first thread and the second thread as responsible for the concurrency bug.Type: GrantFiled: August 26, 2015Date of Patent: August 20, 2019Assignee: Intel corporationInventors: Youfeng Wu, Justin Gottschlich, Gilles Pokam, Shiliang Hu, Ali-Reza Adl-Tabatabai, Cristiano Pereira
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Patent number: 10120781Abstract: Various embodiments are generally directed to detecting race conditions arising from uncoordinated data accesses by different portions of an application routine by detecting occurrences of a selected cache event associated with such accesses. An apparatus includes a processor component; a trigger component for execution by the processor component to configure a monitoring unit of the processor component to detect a cache event associated with a race condition between accesses to a piece of data and to capture an indication of a state of the processor component to generate monitoring data in response to an occurrence of the cache event; and a counter component for execution by the processor component to configure a counter of the monitoring unit to enable capture of the indication of the state of the processor component at a frequency less than every occurrence of the cache event. Other embodiments are described and claimed.Type: GrantFiled: December 12, 2013Date of Patent: November 6, 2018Assignee: INTEL CORPORATIONInventors: Shiliang Hu, Gilles A. Pokam, Cristiano L. Pereira, Justin E. Gottschlich
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Patent number: 10007549Abstract: An apparatus and method are described for a hardware transactional memory (HTM) profiler. For example, one embodiment of an apparatus comprises a transactional debugger (TDB) recording module to record data related to the execution of transactional memory program code, including data related to the execution of branches and transactional events in the transactional memory program code; and a profiler to analyze portions of the recorded data using trace-based replay techniques to responsively generate profile data comprising transaction-level events and function-level conflict data usable to optimize the transactional memory program code.Type: GrantFiled: December 23, 2014Date of Patent: June 26, 2018Assignee: Intel CorporationInventors: Justin E. Gottschlich, Gilles A. Pokam, Shiliang Hu
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Patent number: 9965320Abstract: A processor is described comprising memory access conflict detection circuitry to identify a conflict pertaining to a transaction being executed by a thread that believes it has locked information within a memory. The processor also includes logging circuitry to construct and report out a packet if the memory access conflict detection circuitry identifies a conflict that causes the transaction to be aborted.Type: GrantFiled: December 27, 2013Date of Patent: May 8, 2018Assignee: INTEL CORPORATIONInventors: Rolf Kassa, Justin E. Gottschlich, Shiliang Hu, Gilles A. Pokam, Robert C. Knauerhase
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Patent number: 9875108Abstract: A system, processor, and method to record the interleavings of shared memory accesses in the presence of complex multi-operation instructions. An extension to instruction atomicity (IA) is disclosed that makes it possible for software to infer partial information about a multi-operation execution if the hardware has recorded a dependency due to an instruction atomicity violation (IAV). By monitoring the progress of a multi-operation instruction, the need for complex multi-operation emulation is unnecessary.Type: GrantFiled: March 16, 2013Date of Patent: January 23, 2018Assignee: Intel CorporationInventors: Gilles A. Pokam, Rolf Kassa, Klaus Danne, Tim Kranich, Cristiano L. Pereira, Justin E. Gottschlich, Shiliang Hu
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Patent number: 9817644Abstract: An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.Type: GrantFiled: September 28, 2015Date of Patent: November 14, 2017Assignee: Intel CorporationInventors: Mauricio Breternitz, Jr., Youfeng Wu, Cheng Wang, Edson Borin, Shiliang Hu, Craig B. Zilles
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Publication number: 20170286111Abstract: A processor includes a front end including circuitry to receive an instruction to monitor execution of a thread, a decoder including circuitry to decode the instruction, a scheduler including circuitry to schedule the instruction, a retirement unit including circuitry to retire the instruction, and a core. The core includes circuitry to, based on execution of the instruction, monitor execution of the thread, identify an attempted read of an address during execution of the thread, determine whether a value at the address was previously read during monitoring of the execution of the thread, log the attempted read based on a determination that the value at the address was not previously read during monitoring of the execution of the thread, and omit logging of the attempted read based on a determination that the value at the address was previously read during monitoring of the execution of the thread.Type: ApplicationFiled: April 1, 2016Publication date: October 5, 2017Inventors: Cristiano L. Pereira, Gilles A. Pokam, Shiliang Hu, Beeman C. Strong
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Patent number: 9697040Abstract: A system is disclosed that includes a processor and a dynamic random access memory (DRAM). The processor includes a hybrid transactional memory (HyTM) that includes hardware transactional memory (HTM), and a program debugger to replay a program that includes an HTM instruction and that has been executed has been executed using the HyTM. The program debugger includes a software emulator that is to replay the HTM instruction by emulation of the HTM. Other embodiments are disclosed and claimed.Type: GrantFiled: March 26, 2014Date of Patent: July 4, 2017Assignee: Intel CorporationInventors: Justin E. Gottschlich, Gilles A. Pokam, Shiliang Hu, Rolf Kassa, Youfeng Wu, Irina Calciu
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Publication number: 20170039070Abstract: A mechanism is described for facilitating dynamic and efficient management of instruction atomicity violations in software programs according to one embodiment. A method of embodiments, as described herein, includes receiving, at a replay logic from a recording system, a recording of a first software thread running a first macro instruction, and a second software thread running a second macro instruction. The first software thread and the second software thread are executed by a first core and a second core, respectively, of a processor at a computing device. The recording system may record interleavings between the first and second macro instructions. The method includes correctly replaying the recording of the interleavings of the first and second macro instructions precisely as they occurred. The correctly replaying may include replaying a local memory state of the first and second macro instructions and a global memory state of the first and second software threads.Type: ApplicationFiled: October 19, 2016Publication date: February 9, 2017Inventors: NATHAN D. DAUTENHAHN, JUSTIN GOTTSCHLICH, GILLES POKAM, CRISTIANO PEREIRA, SHILIANG HU, KLAUS DANNE, ROLF KASSA
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Patent number: 9501135Abstract: Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.Type: GrantFiled: January 31, 2014Date of Patent: November 22, 2016Assignee: Intel CorporationInventors: Youfeng Wu, Shiliang Hu, Edson Borin, Cheng Wang
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Patent number: 9501340Abstract: A mechanism is described for facilitating dynamic and efficient management of instruction atomicity violations in software programs according to one embodiment. A method of embodiments, as described herein, includes receiving, at a replay logic from a recording system, a recording of a first software thread running a first macro instruction, and a second software thread running a second macro instruction. The first software thread and the second software thread are executed by a first core and a second core, respectively, of a processor at a computing device. The recording system may record interleavings between the first and second macro instructions. The method includes correctly replaying the recording of the interleavings of the first and second macro instructions precisely as they occurred. The correctly replaying may include replaying a local memory state of the first and second macro instructions and a global memory state of the first and second software threads.Type: GrantFiled: March 15, 2013Date of Patent: November 22, 2016Assignee: Intel CorporationInventors: Nathan D. Dautenhahn, Justin E. Gottschlich, Gilles Pokam, Cristiano L. Pereira, Shiliang Hu, Klaus Danne, Rolf Kassa
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Publication number: 20160299760Abstract: One or more embodiments may provide a method for performing a replay. The method includes initiating execution of a program, the program having a plurality of sets of instructions, and each set of instructions has a number of chunks of instructions. The method also includes intercepting, by a virtual machine unit executing on a processor, an instruction of a chunk of the number of chunks before execution. The method further includes determining, by a replay module executing on the processor, whether the chunk is an active chunk, and responsive to the chunk being the active chunk, executing the instruction.Type: ApplicationFiled: April 18, 2016Publication date: October 13, 2016Applicant: Intel CorporationInventors: Justin E. Gottschlich, Klaus Danne, Cristiano L. Pereira, Gilles A. Pokam, Rolf Kassa, Shiliang Hu, Tim Kranich