Patents by Inventor SHILIANG JI

SHILIANG JI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11393685
    Abstract: The present disclosure provides a method for forming a semiconductor structure. The method includes providing a to-be-etched layer; forming a plurality of initial sidewall spacers on the to-be-etched layer; and performing at least one modification treatment process on the plurality of initial sidewall spacers to form a plurality of sidewall spacers. Each of the at least one modification treatment process includes modifying the plurality of initial sidewall spacers to form a transition layer on the top and sidewall surfaces of each initial sidewall spacer of the plurality of initial sidewall spacers, and then removing the transition layer.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: July 19, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Bo Su, Shiliang Ji, Erhu Zheng, Yan Wang, Haiyang Zhang
  • Publication number: 20220148880
    Abstract: A semiconductor structure and a method for fabricating the semiconductor structure are provided in the present disclosure. The method includes providing a substrate, wherein the substrate includes a plurality of first regions to-be-etched extending along a first direction; a first region to-be-etched includes a central region and an edge region adjacent to each of two sides of the central region; and a material layer to-be-etched is on the substrate; forming a plurality of discrete initial mask structures on the material layer to-be-etched; etching initial mask structures at the edge region till a surface of the material layer to-be-etched is exposed to form a plurality of mask structures; using the plurality of mask structures as a mask, etching the material layer to-be-etched to form a plurality of discrete layers to-be-etched; and removing layers to-be-etched at the central region till a surface of the substrate is exposed.
    Type: Application
    Filed: November 12, 2021
    Publication date: May 12, 2022
    Inventors: Zhenyang Zhao, Shiliang Ji
  • Patent number: 11329144
    Abstract: Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate having a first region; forming a plurality of first initial fin structures on the first region of the semiconductor substrate; forming a dummy gate structure across the first initial fin structures by covering portions of top and sidewall surfaces of the first initial fin structures; forming a dielectric layer covering sidewall surfaces of the dummy gate structure and exposing a top surface of the dummy gate structure; removing the dummy gate structure to form a first opening in the dielectric layer and expose portions of top and sidewall surfaces of the first initial fin structures; and performing at least one trimming process on the first initial fin structures to form fin first structures. A width of each first fin structure is smaller than a width of each first initial fin structure.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: May 10, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Haiyang Zhang, Shiliang Ji
  • Publication number: 20220028899
    Abstract: Semiconductor structure and method of forming semiconductor structure are provided. The semiconductor structure includes a substrate, a first isolation structure, and a first nanostructure and a second nanostructure on two sides of the first isolation structure. The semiconductor structure also includes a second isolation structure, and a third nanostructure and a fourth nanostructure on two sides of the second isolation structure. A top of the second isolation structure is lower than a top of the first isolation structure. The semiconductor structure also includes a first gate structure and a second gate structure. The first gate structure and the second gate structure expose a top surface of the first isolation structure. The semiconductor structure also includes a third gate structure and a fourth gate structure. The third gate structure and the fourth gate structure are in contact with each other on a top surface of the second isolation structure.
    Type: Application
    Filed: July 19, 2021
    Publication date: January 27, 2022
    Inventors: Jian CHEN, Shiliang JI, Haiyang ZHANG
  • Patent number: 11227939
    Abstract: Semiconductor structure and method of forming a semiconductor structure are provided. A substrate is provided, including a first region and a second region that are adjacent to each other and arranged in a first direction. Fins are disposed on a surface of the substrate at the first region, and first openings are located between adjacent fins. The fins include fins to-be-removed. A first dielectric layer is formed on sidewalls of the fins. The first dielectric layer fills the first openings. A first groove is formed in the substrate at the second region by etching the substrate at the second region using the first dielectric layer as a mask. After forming the first groove, a second groove is formed in the substrate at the first region by removing the fins to-be-removed and a portion of the substrate located at bottoms of the fins to-be-removed.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: January 18, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Shiliang Ji, Haiyang Zhang
  • Publication number: 20210193479
    Abstract: The present disclosure provides a method for forming a semiconductor structure. The method includes providing a target etching layer; sequentially forming an initial mask layer, an anti-reflection layer, and a patterned structure on the target etching layer; performing a first etching process on the anti-reflection layer to remove a surface portion of the anti-reflection layer using the patterned structure as a mask; performing a surface treatment process on the patterned structure; and performing a second etching process on the anti-reflection layer until exposing a surface of the initial mask layer.
    Type: Application
    Filed: September 28, 2020
    Publication date: June 24, 2021
    Inventors: Shiliang JI, Panpan LIU, Haiyang ZHANG
  • Publication number: 20210134595
    Abstract: The present disclosure provides a method for forming a semiconductor structure. The method includes providing a to-be-etched layer; forming a plurality of initial sidewall spacers on the to-be-etched layer; and performing at least one modification treatment process on the plurality of initial sidewall spacers to form a plurality of sidewall spacers. Each of the at least one modification treatment process includes modifying the plurality of initial sidewall spacers to form a transition layer on the top and sidewall surfaces of each initial sidewall spacer of the plurality of initial sidewall spacers, and then removing the transition layer.
    Type: Application
    Filed: September 23, 2020
    Publication date: May 6, 2021
    Inventors: Bo SU, Shiliang JI, Erhu ZHENG, Yan WANG, Haiyang ZHANG
  • Publication number: 20210028007
    Abstract: A method for forming a semiconductor structure includes providing a substrate; forming a gate structure on the substrate, the gate structure extending along a first direction; removing a portion of the gate structure to form a trench in the gate structure, the trench penetrating through the gate structure along a second direction which is different form the first direction; performing a first cleaning treatment process on the trench to remove non-metal residues; and performing a second cleaning treatment process on the trench to remove metal residues.
    Type: Application
    Filed: July 22, 2020
    Publication date: January 28, 2021
    Inventors: Shiliang JI, Bo SU, Haiyang ZHANG
  • Publication number: 20200235228
    Abstract: Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate having a first region; forming a plurality of first initial fin structures on the first region of the semiconductor substrate; forming a dummy gate structure across the first initial fin structures by covering portions of top and sidewall surfaces of the first initial fin structures; forming a dielectric layer covering sidewall surfaces of the dummy gate structure and exposing a top surface of the dummy gate structure; removing the dummy gate structure to form a first opening in the dielectric layer and expose portions of top and sidewall surfaces of the first initial fin structures; and performing at least one trimming process on the first initial fin structures to form fin first structures. A width of each first fin structure is smaller than a width of each first initial fin structure.
    Type: Application
    Filed: December 12, 2019
    Publication date: July 23, 2020
    Inventors: Haiyang ZHANG, Shiliang JI
  • Publication number: 20200219992
    Abstract: Semiconductor structure and method of forming a semiconductor structure are provided. A substrate is provided, including a first region and a second region that are adjacent to each other and arranged in a first direction. Fins are disposed on a surface of the substrate at the first region, and first openings are located between adjacent fins. The fins include fins to-be-removed. A first dielectric layer is formed on sidewalls of the fins. The first dielectric layer fills the first openings. A first groove is formed in the substrate at the second region by etching the substrate at the second region using the first dielectric layer as a mask. After forming the first groove, a second groove is formed in the substrate at the first region by removing the fins to-be-removed and a portion of the substrate located at bottoms of the fins to-be-removed.
    Type: Application
    Filed: January 8, 2020
    Publication date: July 9, 2020
    Inventors: Shiliang JI, Haiyang ZHANG
  • Patent number: 9911593
    Abstract: A method for fabricating an NAND flash memory includes providing a semiconductor substrate with a core region and a peripheral region, forming a plurality of discrete gate stack structures in the core region with neighboring gate stack structures separated by a first dielectric layer. The method further includes forming a flowable dielectric layer on the first dielectric layer and the gate stack structures, and forming a solid dielectric layer through a solidification treatment process performed on the flowable dielectric layer. Voids and seams formed in the top portion of the first dielectric layer are filled by the solid dielectric layer. The method also includes removing the solid dielectric layer and a portion of the first dielectric layer to expose a top portion of the gate stack structures, and forming a metal silicide layer on each gate stack structure.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: March 6, 2018
    Assignees: SEIMCONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Erhu Zheng, Shiliang Ji, Yiying Zhang
  • Publication number: 20170170011
    Abstract: A method for fabricating an NAND flash memory includes providing a semiconductor substrate with a core region and a peripheral region, forming a plurality of discrete gate stack structures in the core region with neighboring gate stack structures separated by a first dielectric layer. The method further includes forming a flowable dielectric layer on the first dielectric layer and the gate stack structures, and forming a solid dielectric layer through a solidification treatment process performed on the flowable dielectric layer. Voids and seams formed in the top portion of the first dielectric layer are filled by the solid dielectric layer. The method also includes removing the solid dielectric layer and a portion of the first dielectric layer to expose a top portion of the gate stack structures, and forming a metal silicide layer on each gate stack structure.
    Type: Application
    Filed: August 23, 2016
    Publication date: June 15, 2017
    Inventors: ERHU ZHENG, SHILIANG JI, YIYING ZHANG