Abstract: A method performed by one or more processing resources of one or more computer systems is disclosed. The method comprises receiving an object at a first of a plurality of nodes from a second of the plurality of storage nodes within a cluster switch fabric, examining a value associated included within the received object, wherein the value is associated with a clock value of the second node and updating a clock operating at the first node with the received value.

Abstract: A method performed by one or more processing resources of one or more computer systems is disclosed. The method comprises receiving an object at a first of a plurality of nodes from a second of the plurality of storage nodes within a cluster switch fabric, examining a value associated included within the received object, wherein the value is associated with a clock value of the second node and updating a clock operating at the first node with the received value.

Abstract: The present subject matter relates to systems and methods for assortment planning and optimization in a retail environment. In one implementation, a method for assortment planning and optimization is described. The method includes receiving assortment parameter data, and input information. The input information includes performance data, product data, fixture data and store data. Further, the method includes ranking product items based at least on the assortment parameter data and the input information. Furthermore, the method includes creating a listing of the product items based at least on the ranking. Such listing of the product items is processed based at least on predefined business rules, to generate one or more assortment solutions for providing optimal gross margins.

Abstract: A programmable logic circuit (10) receives a single-ended input signal at a D input (12). An input gate (14) of the programmable logic circuit has a first input connected to the D input, and a second input connected to a D bar input (16). An internal reference (18,22) is programmed to receive a reference level at the D bar input via a programmable external pin (24,26). The internal reference programmed corresponds to the single-ended input signal received at the D input. The internal reference can be a VBB reference level connected to the D bar input providing a reference level to an ECL single-ended input signal on the D input. A CMOS single-ended input signal received at the D input requires a CMOS reference level programmed at the D bar input from the internal reference. An internal selector (72) is also used to select at a pin (76) the corresponding internal reference.