Abstract: A nonvolatile memory device capable of: preventing variations in current and transistor properties to prevent data readout errors; facilitating design changes with a simplified adjustment of the current ratio of transistors; and achieving increased data reading speed.

Abstract: A nonvolatile memory device capable of: preventing variations in current and transistor properties to prevent data readout errors; facilitating design changes with a simplified adjustment of the current ratio of transistors; and achieving increased data reading speed.

Abstract: A nonvolatile memory device capable of: preventing variations in current and transistor properties to prevent data readout errors; facilitating design changes with a simplified adjustment of the current ratio of transistors; and achieving increased data reading speed.

Abstract: A nonvolatile memory device capable of: preventing variations in current and transistor properties to prevent data readout errors; facilitating design changes with a simplified adjustment of the current ratio of transistors; and achieving increased data reading speed.

Abstract: In a DDR operation mode, (L?1) count signal BRDYB is inverted to a low level when 1 is subtracted from initial latency (e.g., L=3). As a result, a delayed signal S (N1BD)/S (N1D) in reverse phase to signal S (N1)/S (N1B) is provided and internal clock signal CKI becomes high during the high level period of the second cycle. This is operated in synchronization with both edges of the external clock signal CLK, and output of double the frequency is started. In the external clock signal cycle immediately before completion of counting of initial latency in a count period for initial latency, the internal clock signal CKI is changed over to double the frequency. Validity flag RDY is changed to a high level during a second cycle of the double frequency.

Abstract: In the semiconductor device composing MOS transistor on which impurities are added from the surface of a P-type substrate, the region of immediate below a gate layer is the P-type substrate on which the impurities are not added, and first and second MOS devices, having an N-type diffusion layer are provided on the surface region of the P-type substrate circumscribing the gate layer. The gate layer of the first MOS device, and the N-type diffusion layer of the second MOS device are connected, and the N-type diffusion layer of the first MOS device and the gate layer of the second MOS device are connected, and thereby a first capacitive element is composed.

Abstract: In a DDR operation mode, (L?1) count signal BRDYB is inverted to a low level when 1 is subtracted from initial latency (e.g., L=3). As a result, a delayed signal S (N1BD)/S (N1D) in reverse phase to signal S (N1)/S (N1B) is provided and internal clock signal CKI becomes high during the high level period of the second cycle. This is operated in synchronization with both edges of the external clock signal CLK, and output of double the frequency is started. In the external clock signal cycle immediately before completion of counting of initial latency in a count period for initial latency, the internal clock signal CKI is changed over to double the frequency. Validity flag RDY is changed to a high level during a second cycle of the double frequency.